SPRUJ53B April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
Table 27-3 lists the memory-mapped registers for the PMBUS_REGS registers. All register offset addresses not listed in Table 27-3 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | PMBCCR | PMBUS CONTROLLER Mode Control Register | EALLOW | Go |
2h | PMBTXBUF | PMBUS Transmit Buffer | Go | |
4h | PMBRXBUF | PMBUS Receive buffer | Go | |
6h | PMBACK | PMBUS Acknowledge Register | Go | |
8h | PMBSTS | PMBUS Status Register | Go | |
Ah | PMBINTM | PMBUS Interrupt Mask Register | EALLOW | Go |
Ch | PMBTCR | PMBUS TARGET Mode Configuration Register | EALLOW | Go |
Eh | PMBHTA | PMBUS Hold TARGET Address Register | Go | |
10h | PMBCTRL | PMBUS Control Register | EALLOW | Go |
12h | PMBTIMCTL | PMBUS Timing Control Register | EALLOW | Go |
14h | PMBTIMCLK | PMBUS Clock Timing Register | EALLOW | Go |
16h | PMBTIMSTSETUP | PMBUS Start Setup Time Register | EALLOW | Go |
18h | PMBTIMBIDLE | PMBUS Bus Idle Time Register | EALLOW | Go |
1Ah | PMBTIMLOWTIMOUT | PMBUS Clock Low Timeout Value Register | EALLOW | Go |
1Ch | PMBTIMHIGHTIMOUT | PMBUS Clock High Timeout Value Register | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 27-4 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
RC | R C | Read to Clear |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
PMBCCR is shown in Figure 27-28 and described in Table 27-5.
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PMBUS CONTROLLER Mode Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRC_CALL | GRP_CMD | PEC_ENA | EXT_CMD | CMD_ENA | ||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BYTE_COUNT | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TARGET_ADDR | RW | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-21 | RESERVED | R | 0h | Reserved |
20 | PRC_CALL | R/W | 0h | 0 = Default state for all messages besides Process Call message 1 = Enables transmission of Process Call message Reset type: SYSRSn |
19 | GRP_CMD | R/W | 0h | 0 = Default state for all messages besides Group Command message 1 = Enables transmission of Group Command message Reset type: SYSRSn |
18 | PEC_ENA | R/W | 0h | 0 = Disables PEC processing 1 = Enables PEC byte transmission/reception Reset type: SYSRSn |
17 | EXT_CMD | R/W | 0h | 0 = Use 1 byte for Command Code 1 = Use 2 bytes for Command Code Reset type: SYSRSn |
16 | CMD_ENA | R/W | 0h | 0 = Disables use of command code on CONTROLLER initiated messages 1 = Enables use of command code on CONTROLLER initiated messages Reset type: SYSRSn |
15-8 | BYTE_COUNT | R/W | 0h | Indicates number of data bytes transmitted in current message. Byte count does not include any device addresses, command words or block lengths in block messages. In block messages, the PMBus Interface automatically inserts the block length into the message based on the byte count setting. The firmware only needs to load the address, command words and data to be transmitted. PMBus Interface supports byte writes up to 255 bytes. Reset type: SYSRSn |
7-1 | TARGET_ADDR | R/W | 0h | Specifies the address of the TARGET to which the current message is directed towards. Reset type: SYSRSn |
0 | RW | R/W | 0h | 0 = Message is a write transaction (data from CONTROLLER to TARGET) 1 = Message is a read transaction (data from TARGET to CONTROLLER) Reset type: SYSRSn |
PMBTXBUF is shown in Figure 27-29 and described in Table 27-6.
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PMBUS Transmit Buffer
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXDATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TXDATA | R/W | 0h | Bits 31-24: BYTE3 - Last data byte transmitted from Transmit Data Buffer Bits 23-16: BYTE2 - Third data byte transmitted from Transmit Data Buffer Bits 15-8: BYTE1 - Second data byte transmitted from Transmit Data Buffer Bits 7-0: BYTE0 - First data byte transmitted from Transmit Data Buffer Reset type: SYSRSn |
PMBRXBUF is shown in Figure 27-30 and described in Table 27-7.
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PMBUS Receive buffer
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXDATA | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RXDATA | R | 0h | Bits 31-24: BYTE3 - Last data byte received in Receive Data Buffer Bits 23-16: BYTE2 - Third data byte received in Receive Data Buffer Bits 15-8: BYTE1 - Second data byte received in Receive Data Buffer Bits 7-0: BYTE0 - First data byte received in Receive Data Buffer Reset type: SYSRSn |
PMBACK is shown in Figure 27-31 and described in Table 27-8.
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PMBUS Acknowledge Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ACK | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | ACK | R/W | 0h | 0 = NACK received data 1 = Acknowledge received data, bit clears upon issue of ACK on PMBus Reset type: SYSRSn |
PMBSTS is shown in Figure 27-32 and described in Table 27-9.
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PMBUS Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | SCL_RAW | SDA_RAW | CONTROL_RAW | ALERT_RAW | CONTROL_EDGE | ALERT_EDGE | |
R-0h | R-1h | R-1h | R-0h | R-1h | RC-0h | RC-0h | |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CONTROLLER | LOST_ARB | BUS_FREE | UNIT_BUSY | RPT_START | TARGET_ADDR_READY | CLK_HIGH_DETECTED | CLK_LOW_TIMEOUT |
RC-0h | RC-0h | RC-0h | RC-0h | RC-0h | RC-0h | RC-0h | RC-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PEC_VALID | NACK | EOM | DATA_REQUEST | DATA_READY | RD_BYTE_COUNT | ||
RC-0h | RC-0h | RC-0h | RC-0h | RC-0h | RC-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | RESERVED | R | 0h | Reserved |
21 | SCL_RAW | R | 1h | 0 = PMBus clock pin observed at logic level low 1 = PMBus clock pin observed at logic level high Reset type: SYSRSn |
20 | SDA_RAW | R | 1h | 0 = PMBus data pin observed at logic level low 1 = PMBus data pin observed at logic level high Reset type: SYSRSn |
19 | CONTROL_RAW | R | 0h | 0 = Control pin observed at logic level low 1 = Control pin observed at logic level high Reset type: SYSRSn |
18 | ALERT_RAW | R | 1h | 0 = Alert pin observed at logic level low 1 = Alert pin observed at logic level high Reset type: SYSRSn |
17 | CONTROL_EDGE | RC | 0h | 0 = Control pin has not transitioned 1 = Control pin has been asserted by another device on PMBus Reset type: SYSRSn |
16 | ALERT_EDGE | RC | 0h | 0 = Alert pin has not transitioned 1 = Alert pin has been asserted by another device on PMBus Reset type: SYSRSn |
15 | CONTROLLER | RC | 0h | 0 = PMBus Interface in TARGET Mode or Idle Mode 1 = PMBus Interface in CONTROLLER Mode Reset type: SYSRSn |
14 | LOST_ARB | RC | 0h | 0 = CONTROLLER has attained control of PMBus 1 = CONTROLLER has lost arbitration and control of PMBus Reset type: SYSRSn |
13 | BUS_FREE | RC | 0h | 0 = PMBus processing current message 1 = PMBus available for new message Reset type: SYSRSn |
12 | UNIT_BUSY | RC | 0h | 0 = PMBus Interface is idle, ready to transmit/receive message 1 = PMBus Interface is busy, processing current message Reset type: SYSRSn |
11 | RPT_START | RC | 0h | 0 = No Repeated Start received by interface 1 = Repeated Start condition received by interface Reset type: SYSRSn |
10 | TARGET_ADDR_READY | RC | 0h | 0 = Indicates no TARGET address is available for reading 1 = TARGET address ready to be read from Receive Data Register (Bits 6:0) Reset type: SYSRSn |
9 | CLK_HIGH_DETECTED | RC | 0h | 0 = No Clock High condition detected 1 = Clock High exceeded 50us during message Reset type: SYSRSn |
8 | CLK_LOW_TIMEOUT | RC | 0h | 0 = No clock low timeout detected 1 = Clock low timeout detected, clock held low for greater than 35ms Reset type: SYSRSn |
7 | PEC_VALID | RC | 0h | 0 = Received PEC not valid (if EOM is asserted) 1 = Received PEC is valid Note: PEC_VALID status is don't care during the message. This will have a valid value only after EOM. Reset type: SYSRSn |
6 | NACK | RC | 0h | 0 = Data transmitted has been accepted by receiver 1 = Receiver has not accepted transmitted data Reset type: SYSRSn |
5 | EOM | RC | 0h | 0 = Message still in progress or PMBus in idle state. 1 = End of current message detected Reset type: SYSRSn |
4 | DATA_REQUEST | RC | 0h | 0 = No data needed by PMBus Interface 1 = PMBus Interface request additional data. PMBus clock stretching enabled to stall bus Reset type: SYSRSn |
3 | DATA_READY | RC | 0h | 0 = No data available for reading by processor 1 = PMBus Interface read buffer full, firmware required to read data prior to further bus activity. PMBus clock stretching enabled to stall bus until data is read by firmware. Reset type: SYSRSn |
2-0 | RD_BYTE_COUNT | RC | 0h | 0 = No received data 1 = 1 byte received. Data located in Receive Data Register, Bits 7-0 2 = 2 bytes received. Data located in Receive Data Register, Bits 15-0 3 = 3 bytes received. Data located in Receive Data Register, Bits 23-0 4 = 4 bytes received. Data located in Receive Data Register, Bits 31-0 Reset type: SYSRSn |
PMBINTM is shown in Figure 27-33 and described in Table 27-10.
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PMBUS Interrupt Mask Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CLK_HIGH_DETECT | LOST_ARB | |||||
R-0h | R/W-1h | R/W-1h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CONTROL | ALERT | EOM | TARGET_ADDR_READY | DATA_REQUEST | DATA_READY | BUS_LOW_TIMEOUT | BUS_FREE |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9 | CLK_HIGH_DETECT | R/W | 1h | 0 = Generates interrupt if clock high exceeds 50us during message 1 = Disables interrupt generation for Clock High detection Reset type: SYSRSn |
8 | LOST_ARB | R/W | 1h | 0 = Generates interrupt upon assertion of Lost Arbitration flag 1 = Disables interrupt generation upon assertion of Lost Arbitration flag Reset type: SYSRSn |
7 | CONTROL | R/W | 1h | 0 = Generates interrupt upon assertion of Control flag 1 = Disables interrupt generation upon assertion of Control flag Reset type: SYSRSn |
6 | ALERT | R/W | 1h | 0 = Generates interrupt upon assertion of Alert flag 1 = Disables interrupt generation upon assertion of Alert flag Reset type: SYSRSn |
5 | EOM | R/W | 1h | 0 = Generates interrupt upon assertion of End of Message flag 1 = Disables interrupt generation upon assertion of End of Message flag Reset type: SYSRSn |
4 | TARGET_ADDR_READY | R/W | 1h | 0 = Generates interrupt upon assertion of TARGET Address Ready flag 1 = Disables interrupt generation upon assertion of TARGET Address Ready flag Reset type: SYSRSn |
3 | DATA_REQUEST | R/W | 1h | 0 = Generates interrupt upon assertion of Data Request flag 1 = Disables interrupt generation upon assertion of Data Request flag Reset type: SYSRSn |
2 | DATA_READY | R/W | 1h | 0 = Generates interrupt upon assertion of Data Ready flag 1 = Disables interrupt generation upon assertion of Data Ready flag Reset type: SYSRSn |
1 | BUS_LOW_TIMEOUT | R/W | 1h | 0 = Generates interrupt upon assertion of Clock Low Timeout flag 1 = Disables interrupt generation upon assertion of Clock Low Timeout flag Reset type: SYSRSn |
0 | BUS_FREE | R/W | 1h | 0 = Generates interrupt upon assertion of Bus Free flag 1 = Disables interrupt generation upon assertion of Bus Free flag Reset type: SYSRSn |
PMBTCR is shown in Figure 27-34 and described in Table 27-11.
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PMBUS TARGET Mode Configuration Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RX_BYTE_ACK_CNT | MAN_CMD | TX_PEC | TX_COUNT | |||
R-0h | R/W-3h | R/W-0h | R/W-0h | R/W-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PEC_ENA | TARGET_MASK | ||||||
R/W-0h | R/W-7Fh | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAN_TARGET_ACK | TARGET_ADDR | ||||||
R/W-0h | R/W-7Ch | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R | 0h | Reserved |
22-21 | RX_BYTE_ACK_CNT | R/W | 3h | Configures number of data bytes to automatically acknowledge when receiving data in TARGET mode. 00 = 1 byte received by TARGET. Firmware is required to manually acknowledge every received byte. 01 = 2 bytes received by TARGET. Hardware automatically acknowledges the first received byte. Firmware is required to manually acknowledge after the second received byte. 10 = 3 bytes received by TARGET. Hardware automatically acknowledges the first 2 received bytes. Firmware is required to manually acknowledge after the third received byte. 11 = 4 bytes received by TARGET. Hardware automatically acknowledges the first 3 received bytes. Firmware is required to manually acknowledge after the fourth received byte Reset type: SYSRSn |
20 | MAN_CMD | R/W | 0h | 0 = TARGET automatically acknowledges received command code 1 = Data Request flag generated after receipt of command code, firmware required to issue ACK to continue message Reset type: SYSRSn |
19 | TX_PEC | R/W | 0h | Asserted when the TARGET needs to send a PEC byte at end of message. PMBus Interface will transmit the calculated PEC byte after transmitting the number of data bytes indicated by TX Byte Cnt(Bits 18:16). Reset type: SYSRSn |
18-16 | TX_COUNT | R/W | 0h | 0 = No bytes valid 1 = One byte valid, Byte #0 (Bits 7:0 of Transmit Data Register) 2 = Two bytes valid, Bytes #0 and #1 (Bits 15:0 of Transmit Data Register) 3 = Three bytes valid, Bytes #0-2 (Bits 23:0 of Transmit Data Register) 4 = Four bytes valid, Bytes #0-3 (Bits 31:0 of Transmit Data Register) Reset type: SYSRSn |
15 | PEC_ENA | R/W | 0h | 0 = PEC processing disabled 1 = PEC processing enabled Reset type: SYSRSn |
14-8 | TARGET_MASK | R/W | 7Fh | Used in address detection, the TARGET mask enables acknowledgement of multiple device addresses by the TARGET. Writing a '0' to a bit within the TARGET mask enables the corresponding bit in the TARGET address to be either '1' or '0' and still allow for a match. Writing a '0' to all bits in the mask enables the PMBus Interface to acknowledge any device address. Upon power-up, the TARGET mask defaults to 7Fh, indicating the TARGET will only acknowledge the address programmed into the TARGET Address (Bits 6-0). Reset type: SYSRSn |
7 | MAN_TARGET_ACK | R/W | 0h | 0 = TARGET automatically acknowledges device address specified in TARGET_ADDR, Bits 6:0 1 = Enables the Manual TARGET Address Acknowledgement Mode. Firmware is required to read received address and acknowledge on every message Note: When bit 31 (I2C_mode) of PMBCTRL register is set it is recommended to use manual acknowledging of TARGET address only (MAN_TARGET_ACK =1). Reset type: SYSRSn |
6-0 | TARGET_ADDR | R/W | 7Ch | Configures the current device address of the TARGET. Used in automatic TARGET address acknowledge mode (default mode). The PMBus Interface will compare the received device address with the value stored in the TARGET Address bits and the mask configured in the TARGET Mask bits. If matching, the TARGET will acknowledge the device address. Reset type: SYSRSn |
PMBHTA is shown in Figure 27-35 and described in Table 27-12.
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PMBUS Hold TARGET Address Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TARGET_ADDR | TARGET_RW | ||||||
R-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-1 | TARGET_ADDR | R | 0h | Stored device address acknowledged by the TARGET Reset type: SYSRSn |
0 | TARGET_RW | R | 0h | Stored R/W bit from address acknowledged by the TARGET 0 = Write Access 1 = Read Access Reset type: SYSRSn |
PMBCTRL is shown in Figure 27-36 and described in Table 27-13.
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PMBUS Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
I2CMODE | ZH_EN | RESERVED | CLKDIV | ||||
R/W-0h | R/W-0h | R-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CLKDIV | CONTROLLER_EN | TARGET_EN | CLK_LO_DIS | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SDA_DIR | SDA_VALUE | SDA_MODE | CNTL_DIR | CNTL_VALUE | CNTL_MODE | ALERT_DIR |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ALERT_VALUE | ALERT_MODE | CNTL_INT_EDGE | FAST_MODE_PLUS | FAST_MODE | BUS_LO_INT_EDGE | ALERT_EN | RESET |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | I2CMODE | R/W | 0h | 0 = PMBUS mode 1 = I2C mode Reset type: SYSRSn |
30 | ZH_EN | R/W | 0h | PMBus Zero data Hold Time Enable 0: PMBus Zero Hold Time Disabled. Doesn't support zero hold time mentioned in SMBus3.0 specification. 1: PMBus Zero Hold Time Enable. Supports zero hold time mentioned in SMBus3.0 specification Reset type: SYSRSn |
29-28 | RESERVED | R | 0h | Reserved |
27-23 | CLKDIV | R/W | 0h | The clock to the PMBUS transmit/receive FSMs (FSM_CLK) is divided version of the SYSCLK clock. Frequency(FSM_CLK) = Frequency(SYSCLK)/(CLKDIV+1) Note: FSM_CLK should be less than (or) equal to 10MHz in standard and fast mode. FSM_CLK should be between 20-25MHz in fast mode plus. Reset type: SYSRSn |
22 | CONTROLLER_EN | R/W | 0h | 0 = Disables PMBus CONTROLLER capability 1 = Enables PMBus CONTROLLER capability Reset type: SYSRSn |
21 | TARGET_EN | R/W | 1h | 0 = Disables PMBus TARGET capability 1 = Enables PMBus TARGET capability Reset type: SYSRSn |
20 | CLK_LO_DIS | R/W | 0h | 0 = Clock Low Timeout Enabled 1 = Clock Low Timeout Disabled Reset type: SYSRSn |
19 | RESERVED | R/W | 0h | Reserved |
18 | RESERVED | R/W | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15 | RESERVED | R/W | 0h | Reserved |
14 | SDA_DIR | R/W | 0h | 0 = PMBus data pin configured as output 1 = PMBus data pin configured as input Reset type: SYSRSn |
13 | SDA_VALUE | R/W | 0h | 0 = PMBus data pin driven low in GPIO Mode 1 = PMBus data pin driven high in GPIO Mode Reset type: SYSRSn |
12 | SDA_MODE | R/W | 0h | 0 = PMBus data pin driven low in GPIO Mode 1 = PMBus data pin driven high in GPIO Mode Reset type: SYSRSn |
11 | CNTL_DIR | R/W | 0h | 0 = Control pin configured as output 1 = Control pin configured as input Reset type: SYSRSn |
10 | CNTL_VALUE | R/W | 0h | 0 = Control pin driven low in GPIO Mode 1 = Control pin driven high in GPIO Mode Reset type: SYSRSn |
9 | CNTL_MODE | R/W | 0h | 0 = Control pin configured in functional mode (Default) 1 = Control pin configured as GPIO Reset type: SYSRSn |
8 | ALERT_DIR | R/W | 0h | 0 = Alert pin configured as output 1 = Alert pin configured as input Reset type: SYSRSn |
7 | ALERT_VALUE | R/W | 0h | 0 = Alert pin driven low in GPIO Mode 1 = Alert pin driven high in GPIO Mode Reset type: SYSRSn |
6 | ALERT_MODE | R/W | 0h | 0 = Alert pin configured in functional mode 1 = Aler3 pin configured as GPIO Reset type: SYSRSn |
5 | CNTL_INT_EDGE | R/W | 0h | 0 = Interrupt generated on falling edge of Control 1 = Interrupt generated on rising edge of Control Reset type: SYSRSn |
4 | FAST_MODE_PLUS | R/W | 0h | 0 = Standard 100 KHz mode enabled 1 = Fast Mode Plus enabled (1MHz operation on PMBus) Reset type: SYSRSn |
3 | FAST_MODE | R/W | 0h | 0 = Standard 100 KHz mode enabled 1 = Fast Mode enabled (400KHz operation on PMBus) Reset type: SYSRSn |
2 | BUS_LO_INT_EDGE | R/W | 0h | 0 = Interrupt generated on rising edge of clock low timeout 1 = Interrupt generated on falling edge of clock low timeout Reset type: SYSRSn |
1 | ALERT_EN | R/W | 0h | 0 = PMBus Alert is not driven by TARGET, pulled up high on PMBus 1 = PMBus Alert driven low by TARGET Reset type: SYSRSn |
0 | RESET | R/W | 0h | 0 = No reset of internal state machines (Default) 1 = Control state machines are reset to initial states Note: Status register PMBSTS should be explicitly cleared by reading the register after softrest as this will not be cleared by Software Reset. Reset type: SYSRSn |
PMBTIMCTL is shown in Figure 27-37 and described in Table 27-14.
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PMBUS Timing Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIM_OVERRIDE | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | TIM_OVERRIDE | R/W | 0h | 0 PMBUS FSMs uses the default settings of the timing parameters. 1 PMBUS FSMs would use the settings in following registers: * PMBTIMCLK * PMBTIMSTSETUP * PMBTIMBIDLE * PMBTIMLOWTIMOUT * PMBTIMHIGHTIMOUT Reset type: SYSRSn |
PMBTIMCLK is shown in Figure 27-38 and described in Table 27-15.
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PMBUS Clock Timing Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CLK_FREQ | ||||||||||||||
R-0h | R/W-60h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLK_HIGH_LIMIT | ||||||||||||||
R-0h | R/W-2Fh | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23-16 | CLK_FREQ | R/W | 60h | Defines the number of PMBUS FSM input clock in the PMBUS CONTROLLER clock period. Number of FSM clocks in the one clock period = (CLK_FREQ+4) Reset type: SYSRSn |
15-8 | RESERVED | R | 0h | Reserved |
7-0 | CLK_HIGH_LIMIT | R/W | 2Fh | Defines the number of PMBUS FSM input clock in the PMBUS CONTROLLER clock high pulse. Number of FSM clocks in the one clock high pulse = (CLK_HIGH_LIMIT+3) Reset type: SYSRSn |
PMBTIMSTSETUP is shown in Figure 27-39 and described in Table 27-16.
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PMBUS Start Setup Time Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TSU_STA | ||||||||||||||||||||||||||||||
R-0h | R/W-2Fh | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | TSU_STA | R/W | 2Fh | Determines the Setup time between last rise edge of the PMBUS CONTROLLER clock and the next start edge, TSU_STA value defines the setup time in terms of PMBUS FSM clock cycles. Reset type: SYSRSn |
PMBTIMBIDLE is shown in Figure 27-40 and described in Table 27-17.
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PMBUS Bus Idle Time Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BUSIDLE | ||||||||||||||||||||||||||||||
R-0h | R/W-1F3h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9-0 | BUSIDLE | R/W | 1F3h | Determines the duration for which PMBUS clock and Data are 1 , to conclude that the bus is IDLE. BUSIDLE value is in terms of number of PMBUS FSM clock cycles. Reset type: SYSRSn |
PMBTIMLOWTIMOUT is shown in Figure 27-41 and described in Table 27-18.
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PMBUS Clock Low Timeout Value Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLKLOWTIMOUT | ||||||||||||||||||||||||||||||
R-0h | R/W-0005572Fh | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19-0 | CLKLOWTIMOUT | R/W | 0005572Fh | Determines the duration for which PMBUS clock if low , will result in a clock low timeout condition. CLKLOWTIMOUT value is in terms of number of PMBUS FSM clock cycles. Reset type: SYSRSn |
PMBTIMHIGHTIMOUT is shown in Figure 27-42 and described in Table 27-19.
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PMBUS Clock High Timeout Value Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLKHIGHTIMOUT | ||||||||||||||
R-0h | R/W-1F3h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9-0 | CLKHIGHTIMOUT | R/W | 1F3h | Determines the duration for which PMBUS clock if high , will result in a clock high timeout condition. CLKHIGHTIMOUT value is in terms of number of PMBUS FSM clock cycles. Reset type: SYSRSn |