SPRUJ53B April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
Table 13-45 lists the memory-mapped registers for the PCTRACE_REGS registers. All register offset addresses not listed in Table 13-45 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | PCTRACE_GLOBAL | PCTRACE_GLOBAL | EALLOW | Go |
2h | PCTRACE_BUFFER | PCTRACE_BUFFER | EALLOW | Go |
4h | PCTRACE_QUAL1 | PCTRACE_QUAL1 | EALLOW | Go |
8h | PCTRACE_QUAL2 | PCTRACE_QUAL2 | EALLOW | Go |
Ch | PCTRACE_LOGPC_SOFTENABLE | PCTRACE_LOGPC_SOFTENABLE | EALLOW | Go |
10h | PCTRACE_LOGPC_SOFTDISABLE | PCTRACE_LOGPC_SOFTDISABLE | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 13-46 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
PCTRACE_GLOBAL is shown in Figure 13-36 and described in Table 13-47.
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Global Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | INIT | ||||||
R-0h | R-0/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EN | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-9 | RESERVED | R | 0h | Reserved |
8 | INIT | R-0/W | 0h | 0 = No action 1 = Trace module is initialized for a fresh trace start with buffer pointer reset and overflow flags cleared along with SOFT_START_PC and SOFT_STOP_PC Reads of this bit position always returns zero Reset type: SYSRSn |
7-1 | RESERVED | R | 0h | Reserved |
0 | EN | R/W | 0h | 0 = PC Trace Disabled 1 = PC Trace Enabled Reset type: SYSRSn |
PCTRACE_BUFFER is shown in Figure 13-37 and described in Table 13-48.
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Trace Buffer pointer register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BUFFER_FULL | RESERVED | PTR | |||||
R-0h | R-0h | R-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PTR | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | BUFFER_FULL | R | 0h | 0 = Trace Buffer Never became full/Overflowed after init 1 = Indicates Trace Buffer became full/Overflowed This bit also gets cleared when INIT is performed via PCTRACE_GLOBAL.INIT Reset type: SYSRSn |
14-10 | RESERVED | R | 0h | Reserved |
9-0 | PTR | R | 0h | Current Pointer to the Trace Buffer. If BUFFER_FULL=0 a. PTR=0 => there is no trace data in buffer ) b. PTR=2,4,6. indicates there is fresh trace data in buffer Buffer pointer gets incremented by 2 for every new trace storage, since two 32-bit values get stored for every discontinuity. For ex : 2 => Locations 0,1 of trace buffer have valid data (SRC,DST) 4 => Locations 0,1,2,3 have valid data (SRC,DST,SRC,DST) and so on If BUFFER_FULL = 1 a. PTR = 0 => buffer is just full b. PTR = non-zero value, then the buffer had overflowed and PTR points to how much it has overflowed. Discontinuities start from PTR (oldest discontinuity trace) to the end of buffer and then follows back to 0 and then until PTR-1(most recent discontinuity trace). This acts more like a circular buffer. These bits also gets cleared when INIT is performed via PCTRACE_GLOBAL.INIT Reset type: SYSRSn |
PCTRACE_QUAL1 is shown in Figure 13-38 and described in Table 13-49.
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Trace Qualifier register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
STOP_INP_SYNCH | STOP_INP_INV | START_INP_SYNCH | START_INP_INV | WINDOWED_INP_SYNCH | WINDOWED_INP_INV | TRACE_MODE | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WINDOWED_INP_SEL | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23 | STOP_INP_SYNCH | R/W | 0h | Enable the 2-stage synchronizer for the selected Stop input Reset type: SYSRSn |
22 | STOP_INP_INV | R/W | 0h | Invert the Selected Stop input Reset type: SYSRSn |
21 | START_INP_SYNCH | R/W | 0h | Enable the 2-stage synchronizer for the selected trace start input Reset type: SYSRSn |
20 | START_INP_INV | R/W | 0h | Invert the Selected Start input Reset type: SYSRSn |
19 | WINDOWED_INP_SYNCH | R/W | 0h | Enable the 2-stage synchronizer for selected trace input Reset type: SYSRSn |
18 | WINDOWED_INP_INV | R/W | 0h | Invert the Selected trace input Reset type: SYSRSn |
17-16 | TRACE_MODE | R/W | 0h | 0x = Trace without any hardware qualifiers 10 = Trace using Windowed mode 11 = Trace using Start/Stop mode These two bits are valid only when PCTRACE_GLOBAL.EN is set to '1' Reset type: SYSRSn |
15-8 | RESERVED | R | 0h | Reserved |
7-0 | WINDOWED_INP_SEL | R/W | 0h | These bits decide which of the inputs will be selected to enable tracing.These inputs will be hooked up to the event outputs from the bus comparator module, counter module and other system events. The usage of these bits are relevant only in the Windowed mode of trace module. Pls refer to the device spec for complete list of signals Reset type: SYSRSn |
PCTRACE_QUAL2 is shown in Figure 13-39 and described in Table 13-50.
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Trace Qualifier register 2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | STOP_INP_SEL | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | START_INP_SEL | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23-16 | STOP_INP_SEL | R/W | 0h | These bits decide which of the inputs will be selected as the STOP event for trace. These inputs will be hooked up to the event outputs from the bus comparator module, counter module and other system events. The usage of these bits are relevant only in the Start/Stop mode of trace module. Pls refer to the device spec for complete list of signals Reset type: SYSRSn |
15-8 | RESERVED | R | 0h | Reserved |
7-0 | START_INP_SEL | R/W | 0h | These bits decide which of the inputs will be selected as the START event for trace. These inputs will be hooked up to the event outputs from the bus comparator module, counter module and other system events. The usage of these bits are relevant only in the Start/Stop mode of trace module. Pls refer to the device spec for complete list of signals Reset type: SYSRSn |
PCTRACE_LOGPC_SOFTENABLE is shown in Figure 13-40 and described in Table 13-51.
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PC when PC Trace was last enabled by software
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PC_SOFTENABLE | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | RESERVED | R | 0h | Reserved |
21-0 | PC_SOFTENABLE | R | 0h | These bits reflect the value of PC when trace module enable bit was last written with '1' (PCTRACE_GLOBAL.EN).These registers are primarily used by ccs drivers while displaying the trace to give a logical start from where tracing was enabled. This register also gets cleared when INIT is performed via PCTRACE_GLOBAL.INIT Reset type: SYSRSn |
PCTRACE_LOGPC_SOFTDISABLE is shown in Figure 13-41 and described in Table 13-52.
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PC when PC Trace was last disabled by software
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PC_SOFTDISABLE | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | RESERVED | R | 0h | Reserved |
21-0 | PC_SOFTDISABLE | R | 0h | These bits reflect the value of PC when trace module enable bit was last written with '0' (PCTRACE_GLOBAL.EN).These registers are primarily used by ccs drivers while displaying the trace to give a logical end to where tracing block was disabled. This register also gets cleared when INIT is performed via PCTRACE_GLOBAL.INIT Reset type: SYSRSn |