The purpose of the CLB tile is to provide
the logic reconfiguration capability of the CLB. The CLB tile contains the following
submodules:
- Counter: The counter submodule can be configured as an adder, a
counter, or a shifter. When functioning as an adder, the counter submodule can either add
or subtract. When functioning as a counter, the counter submodule can count up or count
down. When functioning as a shifter, the counter submodule can shift left or shift right.
The counter event inputs, as well as the reset input, can be freely connected to any of
the other submodules in the same tile. Starting with CLB Type 2, the counter module can also operate as a serializer or linear
feedback shift register. There are three counters in each tile.
- LUT4: The LUT4 submodule has a 4-input look-up table
functionality and is capable of realizing any combinatorial Boolean equation of up to four
inputs. There are three LUT4 submodules in each CLB tile.
- FSM: The Finite State Machine (FSM) submodule can be configured
either as a single four-state finite state machine, or as two independent two-state finite
state machines. The FSM accepts two external inputs, and generates two state outputs and
one combination output. When not used as a state machine, the FSM submodule can accept two
external inputs and function as a 4-input LUT. There are three FSM submodules in each CLB
tile.
- Output LUT: The output LUT is a 3-input lookup table submodule
capable of realizing any combinatorial Boolean equation of up to three inputs. There are
eight such blocks in a CLB tile, each associated with one of the tile outputs.
- Asynchronous Output Conditioning Block: The primary purpose of the Asynchronous
Output Conditioning (AOC) block is to provide asynchronous conditioning capabilities on
the TILE outputs or directly on the inputs of the TILE.
- High Level Controller: The High Level Controller (HLC) submodule
is an event-driven block that can handle up to four concurrent events. The event can be an
activity on any of the other block outputs. A predefined set of operations is executed
when each event occurs. The HLC also provides a data exchange and interrupt mechanism to
the CPU subsystem. There are four working registers (R0, R1, R2, and R3) that can be used
for basic operations, and to modify or set up values for the three counter blocks. Unlike
the other submodules, there is only one HLC in each CLB tile.
- Static Switch Block: The static switch block provides dynamic
connectivity between all of the blocks listed above. Submodules can be connected by the
user, with the only restriction that the submodules must not form a combinational loop
within the tile.
A CLB tile consists of three sets each of
the counter block, FSM, and LUT4, one high-level controller, and eight output LUT blocks.
The submodule numbering is shown in Figure 30-11.
The functionality of the LUT submodules is
configured using a register field containing the binary pattern of the output of the desired
look-up table. For example, a 4-input LUT has 16 possible input permutations, each of which
corresponds to a desired binary 0 or 1 at the output. The register field can, therefore, be
16-bits in length, with each bit representing the desired result of a binary pattern. Input
pattern sequences start at 0000 and continue sequentially to 1111. A similar method is used
to encode the 16-bit state equations in the FSM submodule.