SPRUJ53B April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
Figure 4-2 shows how the Clock Stop module sets and clears the RUNCLOCK signal.
In signal generator modes, GCTL0.SIGGENx_EN bit is cleared when BIT_LENGTH shifts (or rotates) is completed. This makes sure that data is not shifted out. In addition, clock generation (generation of CLKOUT0 to CLKOUT3) also is stopped to make sure that sampling of input data does not continue after BIT_LENGTH shifts when GCTL0.SIGGENx_EN is cleared to 0.
The RUNCLOCK signal has to be high for the clock generation circuitry to be active. When GCTL0.SIGGENx_EN is cleared, the clock generation can be selected to stop on the falling edge of CLKOUT0 to CLKOUT3.
The clock stop module operates as follow: