SPRUJ53B April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
The CLA program code is divided up into tasks or interrupt service routines. Tasks do not have a fixed starting location or length. The CLA program memory can be divided up as desired. The CLA uses the contents of the interrupt vectors (MVECT1 to MVECT8) to determine where a task begins; tasks are terminated by the MSTOP instruction.
The CLA supports eight tasks. Task 1 has the highest priority and task 8 has the lowest priority. The Type-2 CLA offers the option of setting the lowest priority task, for example, task 8, as a background task that, once triggered, runs continuously until the user either terminates the task or resets the CLA or the device. The remaining tasks, 1 through 7, maintain the priority levels and interrupt the background task when triggered.
The background task is enabled by setting the BGEN bit in the MCTLBGRND register; this causes the hardware to disable task 8 in the MIER register. The background task derives the interrupt vector from the MVECTBGRND register instead of MVECT8.
A task can be requested by a peripheral interrupt or by software:
Each task can be triggered by software-selectable interrupt sources. The trigger for each task is defined by writing an appropriate value to the DmaClaSrcSelRegs.CLA1TASKSRCSELx[TASKx] bit field. Each option specifies an interrupt source from a specific peripheral on the shared bus. The peripheral interrupt triggers are listed in Table 7-1.
For example, task 1 (MVECT1) can be set to trigger on EPWMINT1 by writing 36 to DmaClaSrcSelRegs.CLA1TASKSRCSEL1.TASK1. To disable the triggering of a task by a peripheral, set the DmaClaSrcSelRegs.CLA1TASKSRCSELx[TASKx] bit field to 0. Note that a CLA task only triggers on a level transition (an edge) of the configured interrupt source.
Select Value | CLA Trigger Source |
---|---|
0 | CLA_SOFTWARE_TRIGGER |
1 | ADCAINT1 |
2 | ADCAINT2 |
3 | ADCAINT3 |
4 | ADCAINT4 |
5 | ADCA_EVT_INT |
6 | ADCBINT1 |
7 | ADCBINT2 |
8 | ADCBINT3 |
9 | ADCBINT4 |
10 | ADCB_EVT_INT |
11 | ADCCINT1 |
12 | ADCCINT2 |
13 | ADCCINT3 |
14 | ADCCINT4 |
15 | ADCC_EVT_INT |
16 | ADCDINT1 |
17 | ADCDINT2 |
18 | ADCDINT3 |
19 | ADCDINT4 |
20 | ADCD_EVT_INT |
21-28 | Reserved |
29 | XINT1 |
30 | XINT2 |
31 | XINT3 |
32 | XINT4 |
33 | XINT5 |
34-35 | Reserved |
36 | EPWM1_INT |
37 | EPWM2_INT |
38 | EPWM3_INT |
39 | EPWM4_INT |
40 | EPWM5_INT |
41 | EPWM6_INT |
42 | EPWM7_INT |
43 | EPWM8_INT |
44 | EPWM9_INT |
45 | EPWM10_INT |
46 | EPWM11_INT |
47 | EPWM12_INT |
48-51 | Reserved |
52 | MCANA_FEVT0 |
53 | MCANA_FEVT1 |
54 | MCANA_FEVT2 |
55 | MCANB_FEVT0 |
56 | MCANB_FEVT1 |
57 | MCANB_FEVT2 |
58-67 | Reserved |
68 | CPU_TINT0 |
69 | CPU_TINT1 |
70 | CPU_TINT2 |
71-74 | Reserved |
75 | ECAP1_INT |
76 | ECAP2_INT |
77-82 | Reserved |
83 | EQEP1_INT |
84 | EQEP2_INT |
85 | EQEP3_INT |
86-98 | Reserved |
99 | LINA_INT1 |
100 | LINA_INT0 |
101-104 | Reserved |
105 | PMBUSA_INT |
106-108 | Reserved |
109 | SPIA_TXINT |
110 | SPIA_RXINT |
111 | SPIB_TXINT |
112 | SPIB_RXINT |
113-122 | Reserved |
123 | FSITXA_INT1 |
124 | FSITXA_INT2 |
125 | FSIRXA_INT1 |
126 | FSIRXA_INT2 |
127 | CLB1_INT |
128 | CLB2_INT |
129-136 | Reserved |
137 | ADCEINT1 |
138 | ADCEINT2 |
139 | ADCEINT3 |
140 | ADCEINT4 |
141 | ADCE_EVT_INT |
142-183 | Reserved |
184 | DMA_CH1INT |
185 | DMA_CH2INT |
186 | DMA_CH3INT |
187 | DMA_CH4INT |
188 | DMA_CH5INT |
189 | DMA_CH6INT |
CPU software can trigger tasks by writing to the MIFRC register or by the IACK instruction. Using the IACK instruction is more efficient because the instruction does not require the need to issue an EALLOW to set MIFR bits. Set the MCTL[IACKE] bit to enable the IACK feature. Each bit in the operand of the IACK instruction corresponds to a task. For example, IACK #0x0001 sets bit 0 in the MIFR register to start task 1. Likewise, IACK #0x0003 set bits 0 and 1 in the MIFR register to start task 1 and task 2.
The Type-2 CLA allows the use of Task 8 as a background task that runs continuously until Task 8 disables the task or resets the device (or the CLA using a soft reset). The background task vector is given by the MVECTBGRND register and the operation is controlled by the MCTLBGRND register; the task is enabled by setting the BGEN bit to 1. Then start the task through software by writing a 1 to the BGSTART bit (TRIGEN must be 0), or through a peripheral by setting the TRIGEN bit to 1 and then setting the trigger source in the bit-field, DmaClaSrcSelRegs.CLA1TASKSRCSEL2.bit.TASK8. By default, the background task is interruptible; the highest priority pending task is executed first. When a task completes and there are not any pending tasks, the execution returns to the background task. The CLA keeps track of the branching point by saving the return address to the MVECTBGRNDACTIVE register, and then popping this address to the MPC when execution returns. Choose to make sections of the background task uninterruptible by possibly doing this with the MSETC BGINTM assembly instruction.
Subsequently, enabling interrupts with the MCLRC BGINTM instruction.
The background interrupt mask bit, BGINTM, can be queried in the MSTSBGRND register. This register also provides the current status of the background task. If the task is currently executing, the RUN bit is set to 1, if another trigger for the background task is received while the task has already started, the overflow (BGOVF) bit is set.
The CLA has a fetch mechanism and can run and execute a task independently of the CPU. Only one task is serviced at a time; there is no nesting of tasks unless the background task in enabled, then one level of nesting is possible. The task currently running is indicated in the MIRUN register; if the background task is enabled and running, the task is reflected in the MSTSBGRND register (the RUN bit).
Interrupts that have been received but not yet serviced are indicated in the flag register (MIFR). If an interrupt request from a peripheral is received and that same task is already flagged, then the overflow flag bit is set. Overflow flags remain set until the flags are cleared by the CPU. If the CLA is idle (no task is currently running) or is executing the background task, then the highest priority interrupt request that is both flagged (MIFR) and enabled (MIER) starts.
The flow is as follows: