In both multiprocessor modes, the receive sequence is as follows:
- At the receipt of an address block, the SCI port
wakes up and requests an interrupt (bit number 1
RX/BK INT ENA-of SCICTL2 must be enabled to
request an interrupt in non-FIFO mode of
operation. In FIFO mode, RXFFINT serves this
purpose and to enable this, RXFFINTEN in SCIFFRX
register must be enabled with RXFFIL in the same
register set to 1). The SCI reads the first frame
of the block, which contains the destination
address.
- A software routine is entered through the
interrupt and checks the incoming address. This
address byte is checked against the device address
byte stored in memory.
- If the check shows that the block is addressed to the device CPU, the CPU clears the SLEEP bit and reads the rest of the block. If not, the software routine exits with the SLEEP bit still set, and does not receive interrupts until the next block start.