SPRUJ53B April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
This device has HALT, IDLE, and STANDBY as clock-gating low-power modes.
All low-power modes are entered by setting the LPMCR register and executing the IDLE instruction. More information about this instruction can be found in the TMS320C28x CPU and Instruction Set Reference Guide.
Low-power modes must not be entered into while a Flash program or erase operation is ongoing. Entering HALT stops all CPU and peripheral activities. This includes active transmissions and control algorithms. When preparing to enter HALT mode, the application must make sure that the system is prepared to enter a period of inactivity.
Before entering HALT mode, check the value of the GPIODAT register of the pin selected for HALT wake-up (GPIOLPMSEL0/1) prior to entering the low-power mode to make sure that the wake event has not already been asserted.