SPRUJ53B April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
The CLA uses the same address to access data and registers as the main CPU. For example, if the main CPU accesses an ePWM register at address 0x00 6800, then the CLA accesses the register using address 0x6800. Since all CLA accessible memory and registers are within the low 64k x 16 of memory, only the low 16-bits of the address are used by the CLA.
To address the CLA data memory, message RAMs and shared peripherals, the CLA supports two addressing modes:
The CLA does not use a data page pointer or a stack pointer. The two addressing modes are encoded as shown Table 7-8.
Addressing Mode | 'addr' Opcode Field Encode(1) |
Description | ||
---|---|---|---|---|
@dir | 0000 | Direct Addressing Mode | ||
Example 1: MMOV32 MR1, @_VarA | ||||
Example 2: MMOV32 MR1, @_EPwm1Regs.CMPA.all | ||||
In this case, the 'mmmm mmmm mmmm mmmm' opcode field is populated with the 16-bit address of the variable. This is the low 16-bits of the address to access the variable using the main CPU. | ||||
For example, @_VarA populates the address of the variable VarA. and @_EPwm1Regs.CMPA.all populates the address of the CMPA register. | ||||
*MAR0[#imm16]++ | 0001 | MAR0 Indirect Addressing with 16-bit Immediate Post Increment | ||
*MAR1[#imm16]++ | 0010 | MAR1 Indirect Addressing with 16-bit Immediate Post Increment | ||
addr = MAR0 (or MAR1) MAR0 (or MAR1) += #imm16 |
Access memory using the address stored in MAR0 (or
MAR1). Then post increment MAR0 (or MAR1) by #imm16. |
|||
Example 1: MMOV32 MR0, *MAR0[2]++ | ||||
Example 2: MMOV32 MR1, *MAR1[-2]++ | ||||
For a post increment of 0, the assembler accepts both *MAR0 and *MAR0[0]++. | ||||
The 'mmmm mmmm mmmm mmmm' opcode field is populated with the signed 16-bit pointer offset. For example, if #imm16 is 2, then the opcode field is 0x0002. Likewise, if #imm16 is -2, then the opcode field is 0xFFFE. | ||||
If addition of the 16-bit immediate causes overflow, then the value wraps around on a 16-bit boundary. |
Encoding for the shift fields in the MASR32, MLSR32 and MLSL32 instructions is shown in Table 7-9.
Shift Value | 'shift' Opcode Field Encode |
---|---|
1 | 0000 |
2 | 0001 |
3 | 0010 |
.... | .... |
32 | 1111 |
For instructions that use MRx (where x can be 'a' through 'f') as operands, the trailing alphabet appears in the opcode as a two-bit field. For example:
MMPYF32 MRa, MRb, MRc ||
MADDF32 MRd, MRe, MRf
whose opcode is,
LSW: 0000 ffee ddcc bbaa
MSW: 0111 1010 0000 0000
The two-bit field specifies one of four working registers according to Table 7-10.
Two-Bit Field | Working Register |
---|---|
00 | MR0 |
01 | MR1 |
10 | MR2 |
11 | MR3 |
Table 7-11 shows the condition field encoding for conditional instructions such as MNEGF, MSWAPF, MBCNDD, MCCNDD, and MRCNDD.
Encode(1) | CNDF | Description | MSTF Flags Tested |
---|---|---|---|
0000 | NEQ | Not equal to zero | ZF == 0 |
0001 | EQ | Equal to zero | ZF == 1 |
0010 | GT | Greater than zero | ZF == 0 AND NF == 0 |
0011 | GEQ | Greater than or equal to zero | NF == 0 |
0100 | LT | Less than zero | NF == 1 |
0101 | LEQ | Less than or equal to zero | ZF == 1 OR NF == 1 |
1010 | TF | Test flag set | TF == 1 |
1011 | NTF | Test flag not set | TF == 0 |
1100 | LU | Latched underflow | LUF == 1 |
1101 | LV | Latched overflow | LVF == 1 |
1110 | UNC | Unconditional | None |
1111 | UNCF(2) | Unconditional with flag modification | None |