SPRUJ53B April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
The required frequency tolerance for the CAN bit clock depends on the bit timing setup and network configuration, and can be as tight as 0.1%. Since the main system clock (in the form of SYSCLK) can not be precise, the bit clock can also be connected to the AUXCLKIN path using the CLKSRCCTL2 register. There is an independent selection for each CAN module.
To maintain correct operation, the frequency of the CAN bit clock must be less than or equal to the SYSCLK frequency.