The ECC aggregator module aggregates the level
pending status from the ECC RAM into a single EOI-handshake based interrupt to the
Host CPU. Software is expected to follow the sequence described:
- Software enables the interrupts for the ECC RAM
by writing to the MCANERR_SEC_ENABLE_SET/MCANERR_DED_ENABLE_SET register.
- Software writes the ECC RAM ID in the
MCANERR_VECTOR.ECC_VECTOR.
- Software writes the MCANERR_VECTOR.RD_SVBUS bit
to trigger the read.
- Software writes the MCANERR_ERR_STAT1 register
address to the MCANERR_VECTOR.RD_SVBUS_ADDRESS field. Software needs to load the
'read message' in the rMCANERR_VECTOR register again, if the software needs to
read the MCANERR_ERR_STAT2 register.
- Software polls the MCANERR_VECTOR.RD_SVBUS_DONE
bit. When this bit is set, a read of the MCANERR_ERR_STAT1/MCANERR_ERR_STAT2
register is performed.
- After the interrupt has been serviced, software
clears the interrupt status by writing to the MCANERR_ERR_STAT1.CLR_ECC_SEC or
MCANERR_ERR_STAT1.CLR_ECC_DED bit depending on the type of the ECC error.
- Software polls the MCANERR_ERR_STAT1 register to
verify that the status bit has been cleared.
- Software writes to the
MCANERR_SEC_EOI/MCANERR_DED_EOI register to clear the interrupt.
- After clearing the ECC interrupt source, the
application software must also write 1 to the MCANERR_SEC_EOI.EOI_WR
/MCANERR_DED_EOI.EOI_WR bits.