The time-base period register (TBPRD) has a shadow register. Shadowing allows the register update to be synchronized with the hardware. The following definitions are used to describe all shadow registers in the ePWM module:
- Active Register: The active register
controls the hardware and is responsible for
actions that the hardware causes or invokes.
- Shadow Register: The shadow register
buffers provide a temporary holding location for
the active register and have no direct effect on
any control hardware. At a strategic point in
time, the shadow register content is transferred
to the active register. This prevents corruption
or spurious operation due to the register being
asynchronously modified by software.
The memory address of the shadow period register is the same as the active register. Which register is written to or read from is determined by the TBCTL[PRDLD] bit. This bit enables and disables the TBPRD shadow register as follows:
- Time-Base Period Shadow Mode: The TBPRD
shadow register is enabled when TBCTL[PRDLD] = 0.
Reads from and writes to the TBPRD memory address
go to the shadow register. The shadow register
contents are transferred to the active register
(TBPRD (Active) ← TBPRD (shadow)) when the
time-base counter equals zero (TBCTR = 0x00)
and/or a sync event as determined by the
TBCTL2[PRDLDSYNC] bit. The PRDLDSYNC bit is valid
only if TBCTL[PRDLD] = 0. By default the TBPRD
shadow register is enabled. The sources for the
SYNC input is explained in Section 19.4.3.3.
The
global load control mechanism can also be used
with the time-base period register by configuring
the appropriate bits in the global load
configuration register (GLDCFG). When global load
mode is selected the transfer of contents from
shadow register to active register, for all
registers that have this mode enabled, occurs at
the same event as defined by the configuration
bits in Global Shadow to Active Load Control
Register (GLDCTL). Global load control mechanism
is explained in Section 19.4.7.
- Time-Base Period Immediate Load Mode: If
immediate load mode is selected (TBCTL[PRDLD] =
1), then a read from or a write to the TBPRD
memory address goes directly to the active
register.