SPRUJ53B April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
The Rx FIFO blocking mode is the default operation mode for the Rx FIFOs and is configured by MCAN_RXFnC[31].FnOM = 0.
If an Rx FIFO full condition is reached (MCAN_RXFnS[21:16].FnPI = MCAN_RXFnS[13:8].FnGI), no further messages are written to the corresponding Rx FIFO until at least one message has been read out and the Rx FIFO Get Index has been incremented. An Rx FIFO full condition is signaled by the MCAN_RXFnS[24].FnF = 1 and interrupt flag MCAN_IR.RF0F/MCAN_IR.RF1F is set.
In case a message is received while the corresponding Rx FIFO is full, this message is rejected and the message lost condition is signaled by MCAN_RXFnS[25].RFnL = 1 and interrupt flag MCAN_IR.RF0L/MCAN_IR.RF1L is set.