SPRUJ53B April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
The purpose of this chapter is to explain the boot read-only memory (ROM) code functionality for the CPU core, including the boot procedure. This chapter also discusses the functions and features of the boot ROM code, and provides details about the ROM memory-map contents. On every reset, the device executes a boot sequence in the ROM depending on the reset type and boot configuration. This sequence initializes the device to run the application code. For the CPU, the boot ROM also contains peripheral bootloaders that can be used to load an application into RAM. These bootloaders can be disabled for safety or security purposes.
See Table 4-1 for details on available boot features for the C28x CPU. Additionally, Table 4-2 shows the sizes of the various ROMs on the device.
For details on the security APIs provided, refer to Section 4.7.10.
Various tables are provided in ROM for use in software library, refer to Section 4.7.7 for more details.
Boot Feature | CPU |
---|---|
Initial boot process | Device reset |
Boot mode selection | GPIOs |
Boot modes supported |
Flash boot Secure Flash boot Firmware update (FWU) Flash boot RAM boot |
Peripheral boot loaders supported |
Parallel IO SCI / Wait CANFD I2C SPI USB |
ROM | CPU Size |
---|---|
Unsecure boot ROM | 80KB |
Secure ROM | 16KB |
CLA data ROM | 8KB |