SPRUJ53B April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
This example shows how to sample multiple signals with different acquisition window requirements. CPU1 Timer 2 is used to generate the trigger. To see how to configure the CPU timer, see the System Control and Interrupts chapter.
A good first step when designing a sampling scheme with many signals is to list out the signals and the required acquisition window. From this, calculate the necessary number of SYSCLK cycles for each signal, then the ACQPS register setting. This is shown in Table 15-5, where a SYCLK of 150MHz is assumed (6.666ns cycle time).
Signal Name | Acquisition Window Requirement |
Acquisition Window (SYSCLK Cycles) |
ACQPS Register Value |
---|---|---|---|
Signal 1 | >160ns | 160ns/6.666ns = 24 | 24 – 1 = 23 |
Signal 2 | >592ns | 592ns/6.666ns = 89 (round up) | 89 – 1 = 88 |
Signal 3 | >147ns | 147ns/6.666ns = 22 | 22 – 1 = 21 |
Signal 4 | >392ns | 392ns/6.666ns = 59 (round up) | 59 – 1 = 58 |
Next decide which ADC pins to connect to each signal. This is highly dependent on the application board layout. Once the pins are selected, determining the value of CHSEL is straightforward (see Table 15-6).
Signal Name | ADC Pin | CHSEL Register Value |
---|---|---|
Signal 1 | ADCINA5 | 5 |
Signal 2 | ADCINA0 | 0 |
Signal 3 | ADCINA3 | 3 |
Signal 4 | ADCINA2 | 2 |
With the information tabulated, generate the SOC configurations:
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 5; //SOC0 converts ADCINA5
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 23; //SOC0 uses a sample duration of 24 SYSCLK cycles
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 3; //SOC0 begins conversion on CPU1 Timer 2
AdcaRegs.ADCSOC1CTL.bit.CHSEL = 0; //SOC1 converts ADCINA0
AdcaRegs.ADCSOC1CTL.bit.ACQPS = 88; //SOC1 uses a sample duration of 89 SYSCLK cycles
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 3; //SOC1 begins conversion on CPU1 Timer 2
AdcaRegs.ADCSOC2CTL.bit.CHSEL = 3; //SOC2 converts ADCINA3
AdcaRegs.ADCSOC2CTL.bit.ACQPS = 21; //SOC2 uses a sample duration of 22 SYSCLK cycles
AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = 3; //SOC2 begins conversion on CPU1 Timer 2
AdcaRegs.ADCSOC3CTL.bit.CHSEL = 2; //SOC3 converts ADCINA2
AdcaRegs.ADCSOC3CTL.bit.ACQPS = 58; //SOC3 uses a sample duration of 59 SYSCLK cycles
AdcaRegs.ADCSOC3CTL.bit.TRIGSEL = 3; //SOC3 begins conversion on CPU1 Timer 2
As configured, when CPU1 Timer 2 generates an event, SOC0, SOC1, SOC2, and SOC3 eventually is sampled and converted, in that order. The conversion results for ACINA5 (Signal 1) are in ADCRESULT0. Similarly, The results for ADCINA0 (Signal 2), ADCINA3 (Signal 3), and ADCINA2 (Signal 4) are in ADCRESULT1, ADCRESULT2, and ADCRESULT3, respectively.