SPRUJ66B February   2023  – September 2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Key Features
        1. 1.3.1.1 Processor
        2. 1.3.1.2 Memory
        3. 1.3.1.3 JTAG Emulator
        4. 1.3.1.4 Supported Interfaces and Peripherals
        5. 1.3.1.5 Expansion Connectors Headers to Support Application Specific Add On Boards
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 EVM Revisions and Assembly Variants
    2. 2.2 System Description
      1. 2.2.1 Board Image With Markings
      2. 2.2.2 Functional Block Diagram
      3. 2.2.3 AM62A Low Power SK EVM Interface Mapping
      4. 2.2.4 Power ON/OFF Procedures
        1. 2.2.4.1 Power-On Procedure
        2. 2.2.4.2 Power-Off Procedure
        3. 2.2.4.3 Power Test Points
      5. 2.2.5 Peripheral and Major Component Description
        1. 2.2.5.1  Clocking
          1. 2.2.5.1.1 Peripheral Ref Clock
        2. 2.2.5.2  Reset
        3. 2.2.5.3  CSI Interface
        4. 2.2.5.4  Audio Codec Interface
        5. 2.2.5.5  HDMI Display Interface
        6. 2.2.5.6  JTAG Interface
        7. 2.2.5.7  Test Automation Header
        8. 2.2.5.8  UART Interface
        9. 2.2.5.9  USB Interface
          1. 2.2.5.9.1 USB 2 0 Type A Interface
          2. 2.2.5.9.2 USB 2 0 Type C Interface
        10. 2.2.5.10 Memory Interfaces
          1. 2.2.5.10.1 LPDDR4 Interface
          2. 2.2.5.10.2 Octal Serial Peripheral Interface (OSPI)
          3. 2.2.5.10.3 MMC Interfaces
            1. 2.2.5.10.3.1 MMC0 - eMMC Interface
            2. 2.2.5.10.3.2 MMC1 - Micro SD Interface
            3. 2.2.5.10.3.3 MMC2 - M.2 Key E Interface
          4. 2.2.5.10.4 Board ID EEPROM
        11. 2.2.5.11 Ethernet Interface
          1. 2.2.5.11.1 CPSW Ethernet PHY Default Configuration
        12. 2.2.5.12 GPIO Port Expander
        13. 2.2.5.13 GPIO Mapping
        14. 2.2.5.14 Power
          1. 2.2.5.14.1 Power Requirements
          2. 2.2.5.14.2 Power Input
          3. 2.2.5.14.3 Power Supply
          4. 2.2.5.14.4 AM62A SoC Power
          5. 2.2.5.14.5 Current Monitoring
        15. 2.2.5.15 AM62A Low Power SK EVM User Setup and Configuration
          1. 2.2.5.15.1 Boot Modes
          2. 2.2.5.15.2 User Test LEDs
        16. 2.2.5.16 Expansion Headers
          1. 2.2.5.16.1 User Expansion Connector
          2. 2.2.5.16.2 MCU Connector
        17. 2.2.5.17 I2C Address Mapping
  9. 3Hardware Design Files
    1. 3.1 Schematics, PCB Layout and BOM
  10. 4Additional Information
    1. 4.1 Known Hardware or Software Issues
    2. 4.2 EMC, EMI, and ESD Compliance
    3. 4.3 Trademarks
    4.     72
  11. 5Revision History
2.2.5.15.1 Boot Modes

The boot mode for the SK EVM board is defined by two banks of switches SW2 and SW3 or by the I2C buffer connected to the Test automation connector. This allows for AM62A SOC Boot mode control by either the user (DIP Switch Control) or by the Test Automation connector.

All the bits of switch (SW2 and SW3) have weak pull down resistor and a strong pull up resistor as shown in Figure 2-31. Note that OFF setting provides a low logic level (‘0’) and an ON setting provide a high logic level (‘1’).

SK-AM62A-LP Bootmode Switches Figure 2-31 Bootmode Switches

The boot mode pins of the SOC have associated alternate functions during normal operation. Hence, isolation is provided using Buffer IC’s to cater for alternate pin functionality. The output of the buffer is connected to the boot mode pins on the AM62A SOC and the output is enabled only when the boot mode is needed during a reset cycle.

The input to the buffer is connected to the DIP switch circuit and to the output of an I2C IO Expander set by the test automation circuit. If the test automation circuit controls the boot mode, all the switches can be manually set to the OFF position. The boot mode buffer is powered by an always ON power supply to make sure that the boot mode remains present even if the SOC is power cycled.

Switch SW2 and SW3 bits [15:0] are used to set the SOC Boot mode.

The switch map to the boot mode functions is provided in the tables below.

Table 2-16 Bootmode Pin Strapping
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reserved Reserved Backup Boot Mode Configuration Backup Boot Mode Primary Boot Mode Configuration Primary Boot Mode PLL Configuration
Table 2-17 PLL Reference Clock Selection BOOTMODE[2:0]
SW2.3 SW2.2 SW2.1 PLL REF CLK (MHz)
OFF OFF OFF 19.2
OFF OFF ON 20
OFF ON OFF 24
OFF ON ON 25
ON OFF OFF 26
ON OFF ON 27
ON ON OFF RSVD
ON ON ON RSVD
Table 2-18 Boot Device Selection BOOTMODE[6:3]
SW2.7 SW2.6 SW2.5 SW2.4 Primary Boot Device Selected
OFF OFF OFF OFF Serial NAND
OFF OFF OFF ON OSPI
OFF OFF ON OFF QSPI
OFF OFF ON ON SPI
OFF ON OFF OFF Ethernet RGMII
OFF ON OFF ON Ethernet RMII
OFF ON ON OFF I2C
OFF ON ON ON UART
ON OFF OFF OFF MMC/SD card
ON OFF OFF ON eMMC
ON OFF ON OFF USB0
ON OFF ON ON GPMC NAND
ON ON OFF OFF GPMC NOR
ON ON OFF ON Rsvd
ON ON ON OFF xSPI
ON ON ON ON No boot/Dev Boot
Table 2-19 Primary Boot Media Configuration BOOTMODE [9:7]
SW3.2 SW3.1 SW2.8 Boot Device
Reserved Read Mode 2 Read Mode 1 Serial NAND
Reserved Iclk Csel QSPI
Reserved Iclk Csel OSPI
Reserved Mode Csel SPI
Clkout 0 Link Info Ethernet RGMII
Clkout Clk src 0 Ethernet RMII
Bus Reset Reserved Addr I2C
Reserved Reserved Reserved UART
1 Reserved Fs/raw MMC/ SD card
Reserved Reserved Reserved eMMC
Core Volt Mode Lane swap USB0
Reserved Reserved Reserved GPMC NAND
Reserved Reserved Reserved GPMC NOR
Reserved Reserved Reserved Reserved
SFPD Read Cmd Mode xSPI
Reserved ARM/Thumb No/Dev No boot/Dev Boot
Table 2-20 Serial NAND Configuration Fields
BOOTMODE Pins Field Value Description
8 [SW3.1] Read Mode 2 0 Reserved (Read mode is taken from Read Mode 1
1

SPI/ 1-1-1 mode (Read mode is taken from Read

Mode 2 and Read Mode 1 is ignored)
7 [SW2.8] Read Mode 1 0 OSPI/ 1-1-8 Mode (valid only when Read Mode 2 is 0)
1 OSPI/ 1-1-4 Mode (valid only when Read Mode 2 is 0)
Table 2-21 OSPI Boot Configuration Fields
BOOTMODE Pins Field Value Description
7 [SW2.8] Csel 0 Boot Flash is on CS 0
1 Boot Flash is on CS 1
Table 2-22 QSPI Boot Configuration Fields
BOOTMODE Pins Field Value Description
7 [SW2.8] Csel 0 Boot Flash is on CS 0
1 Boot Flash is on CS 1
Table 2-23 SPI Boot Configuration Fields
BOOTMODE Pins Field Value Description
8 [SW3.1] Mode 0 SPI Mode 0
1 SPI Mode 3
7 [SW2.8] Csel 0 Boot Flash is on CS 0
1 Boot Flash is on CS 1
Table 2-24 Ethernet RGMII Boot Configuration Fields
BOOTMODE Pins Field Value Description
9 [SW3.2] Clkout 0 Must be set to 0 to choose external clock
1 Reserved

8 [SW3.1]

Delay 0 Must be set to 0 for RGMII with internal Tx delay
1 Reserved
7 [SW2.8] Link info 0 MDIO PHY scan used for link parameters
1 Link parameters programmed by the ROM
Table 2-25 Ethernet RMII Boot Configuration Fields
BOOTMODE Pins Field Value Description
9 [SW3.2] Clkout 0 50MHz clock not generated on CLKOUT0
1 50MHz clock generated on CLKOUT0

8 [SW3.1]

Clk src 0 External clock source for RMII1_REF_CLK
1 Internal clock source for RMII1_REF_CLK
7 [SW2.8] RMII 0 This bit must be set to 0
1 Reserved
Table 2-26 Ethernet RMII Clocking
BOOTMODE Pin 9 (Clk out) BOOTMODE Pin 8 (Clk src) Description
0 0

50MHz external source to RMII_REF_CLK and to external Ethernet

PHY input clock (CLKOUT0 is unused) These are the recommended

settings
0 1 Not a valid configuration
1 0

CLKOUT0 is configured to 50MHz and connect to both

RMII1_REF_CLK and to external Ethernet PHY input clock
1 1 Not a valid configuration
Table 2-27 Ethernet Backup Boot Configuration Field
BOOTMODE Pins Field Value Description
13 [SW3.2] Interface 0 RGMII with internal TX delay
1 RMII with external clock source
Table 2-28 I2C Boot Configuration Fields
BOOTMODE Pins Field Value Description
9 [SW3.2] Bus reset 0 Hung bus reset attempt after 1ms
1 No hung bus reset attempted
7 [SW2.8] Address 0 EEPROM's address is 0x50
1 EEPROM's address is 0x51
Table 2-29 SD Card Boot Configuration Fields
BOOTMODE Pins Field Value Description

9 [SW3.2]

13(1) [SW3.2]

 Port 0 Reserved
1 MMC Port 1 (4 bit width). This bit must be set to 1
7 [SW2.8] FS/Raw 0 File system mode
1 Raw Mode
(1) When MMCSD is the backup mode
Table 2-30 eMMC Boot Configuration Fields
BOOTMODE Pins Field Value Description

9 [SW3.2]

13(1) [SW3.2]

 Port 0 MMCSD Port 0 (8 bit width). This bit must be set to 0
1 Reserved
7 [SW2.8] FS/Raw 0 Filesystem mode
1 Raw Mode
(1) When MMCSD is the backup mode
Table 2-31 USB Boot Configuration Fields
BOOTMODE Pins Field Value Description
9 [SW3.2] Core Voltage 0 0.85V core voltage
1 0.75V core voltage

8 [SW3.1]

13(1) [SW3.2]

 Mode 0 DFU (USB device firmware upgrade)
1 Host (MSC boot)
7 [SW2.8] Lane Swap 0 D+/D- lines are not swapped
1 D+/D- lines are swapped
(1) When USB is the backup mode.
Table 2-32 xSPI Boot Configuration Fields
BOOTMODE Pins Field Value Description
9 [SW3.2] SFDP 0 SFDP disabled
1 SFDP enabled

8 [SW3.1]

Read cmd 0 0x0B Read Command
1 0xEE Read Command
7 [SW2.8] Mode 0 1S-1S-1S mode @ 50MHz
1 8D-8D-8D mode @ 25MHz
Table 2-33 Backup Bootmode Selection BOOTMODE[12:10]
SW3.5 SW3.4 SW3.3 Backup Boot Device Selected
OFF OFF OFF None(No backup mode)
OFF OFF ON USB
OFF ON OFF Reserved
OFF ON ON UART
ON OFF OFF Ethernet
ON OFF ON MMC/SD
ON ON OFF SPI
ON ON ON I2C