SPRUJ66B February   2023  – September 2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Key Features
        1. 1.3.1.1 Processor
        2. 1.3.1.2 Memory
        3. 1.3.1.3 JTAG Emulator
        4. 1.3.1.4 Supported Interfaces and Peripherals
        5. 1.3.1.5 Expansion Connectors Headers to Support Application Specific Add On Boards
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 EVM Revisions and Assembly Variants
    2. 2.2 System Description
      1. 2.2.1 Board Image With Markings
      2. 2.2.2 Functional Block Diagram
      3. 2.2.3 AM62A Low Power SK EVM Interface Mapping
      4. 2.2.4 Power ON/OFF Procedures
        1. 2.2.4.1 Power-On Procedure
        2. 2.2.4.2 Power-Off Procedure
        3. 2.2.4.3 Power Test Points
      5. 2.2.5 Peripheral and Major Component Description
        1. 2.2.5.1  Clocking
          1. 2.2.5.1.1 Peripheral Ref Clock
        2. 2.2.5.2  Reset
        3. 2.2.5.3  CSI Interface
        4. 2.2.5.4  Audio Codec Interface
        5. 2.2.5.5  HDMI Display Interface
        6. 2.2.5.6  JTAG Interface
        7. 2.2.5.7  Test Automation Header
        8. 2.2.5.8  UART Interface
        9. 2.2.5.9  USB Interface
          1. 2.2.5.9.1 USB 2 0 Type A Interface
          2. 2.2.5.9.2 USB 2 0 Type C Interface
        10. 2.2.5.10 Memory Interfaces
          1. 2.2.5.10.1 LPDDR4 Interface
          2. 2.2.5.10.2 Octal Serial Peripheral Interface (OSPI)
          3. 2.2.5.10.3 MMC Interfaces
            1. 2.2.5.10.3.1 MMC0 - eMMC Interface
            2. 2.2.5.10.3.2 MMC1 - Micro SD Interface
            3. 2.2.5.10.3.3 MMC2 - M.2 Key E Interface
          4. 2.2.5.10.4 Board ID EEPROM
        11. 2.2.5.11 Ethernet Interface
          1. 2.2.5.11.1 CPSW Ethernet PHY Default Configuration
        12. 2.2.5.12 GPIO Port Expander
        13. 2.2.5.13 GPIO Mapping
        14. 2.2.5.14 Power
          1. 2.2.5.14.1 Power Requirements
          2. 2.2.5.14.2 Power Input
          3. 2.2.5.14.3 Power Supply
          4. 2.2.5.14.4 AM62A SoC Power
          5. 2.2.5.14.5 Current Monitoring
        15. 2.2.5.15 AM62A Low Power SK EVM User Setup and Configuration
          1. 2.2.5.15.1 Boot Modes
          2. 2.2.5.15.2 User Test LEDs
        16. 2.2.5.16 Expansion Headers
          1. 2.2.5.16.1 User Expansion Connector
          2. 2.2.5.16.2 MCU Connector
        17. 2.2.5.17 I2C Address Mapping
  9. 3Hardware Design Files
    1. 3.1 Schematics, PCB Layout and BOM
  10. 4Additional Information
    1. 4.1 Known Hardware or Software Issues
    2. 4.2 EMC, EMI, and ESD Compliance
    3. 4.3 Trademarks
    4.     72
  11. 5Revision History
2.2.5.11.1 CPSW Ethernet PHY Default Configuration

The default configuration of the DP83867 is determined using a number of resistor pull-up and pull-down values on specific pins of the PHY. Depending on the values installed, each of the configuration pins can be set to one of four modes. The AM62A Low Power SK EVM uses the 48-pin QFN package which supports the RGMII interface.

The DP83867 PHY uses four level configurations based on resistor strapping which generate four distinct voltages ranges. The resistors are connected to the RX data and control pins which are normally driven by the PHY and are inputs to the processor. The voltage range for each mode is shown below:

Mode1 - 0V to 0.3V

Mode 2 – 0.462V to 0.6303V

Mode3 – 0.7425V to 0.9372V

Mode4 – 2.2902V to 2.9304V

Footprints for both pull-up and pull-down is provided on all the strapping pins except LED_0. LED_0 is for Mirror Enable, which is set to Mode1 by default, Mode4 is not applicable and Mode2, Mode3 option is not desired. The PHY is resistor strapped for the below configurations:

PHY ADDR: 00000

Auto_neg: Enabled

ANG_SEL : 10/100/1000

RGMII TXCLK skew : 0ns

RGMII RXCLK skew : 2ns

Table 2-8 CPSW Ethernet Strap Settings
Strap Setting Pin Name Strap Function Mode Value of Strap Function Description
PHY Address RX_D2 PHY_AD3 1 0 PHY Address: 0000
PHY_AD2 1 0
RX_D0 PHY_AD1 1 0
PHY_AD0 1 0
Auto Negotiation RX_DV/ RX_CTRL Auto- neg 3 0 Autoneg Disable=0
Modes of Operation LED2 RGMII Clock Skew TX[1] 5 0 RGMIITX Clock Skew is set to 0ns
RGMII Clock Skew TX[0] 5 0
LED_1 RGMIIClock Skew TX[2] 5 1
ANEG_SEL 1 0 Advertiseability of 10/100/1000
LED_0 Mirror Enable 1 0 Mirror Enable Disabled
GPIO_1 RGMII Clock Skew RX[2] 1 0 RGMIIRX Clock Skew is set to 2ns
RGMII Clock Skew TX[1] 1 0
GPIO_0 RGMII Clock Skew RX[0] 1 0