SPRUJ70A January   2023  – March 2024 AM69

 

  1.   1
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Inside the Box
    2. 1.2 Key Features and Interfaces
    3. 1.3 Thermal Compliance
    4. 1.4 Electrostatic Discharge (ESD) Compliance
  4. 2User Interfaces
    1. 2.1 Power Input
      1. 2.1.1 Power Input [J24] With LED for Status [LD4]
      2. 2.1.2 Power Budget Considerations
    2. 2.2 User Inputs
      1. 2.2.1 Board Configuration Settings [SW2]
      2. 2.2.2 Reset Pushbutton [SW3]
      3. 2.2.3 User Pushbutton [SW1] With User LED Indication [LD5]
    3. 2.3 Standard Interfaces
      1. 2.3.1 UART-Over-USB [J6] With LED for Status [LD1]
      2. 2.3.2 Gigabit Ethernet [J10] With Integrated LEDs for Status
      3. 2.3.3 On-Board JTAG/Emulator [J13] with optional External Interface [J15]
      4. 2.3.4 USB3.1 Gen1 Interfaces [J11] [J14]
      5. 2.3.5 Stacked DisplayPort and HDMI Type A [J16]
      6. 2.3.6 PCIe Connector [J3] for PCIe Card Modules
      7. 2.3.7 M.2 Key M Connector [J12] for SSD Modules
      8. 2.3.8 M.2 Key E Connector [J23] for Wi-Fi Networking Modules
      9. 2.3.9 MicroSD Card Cage [J32]
    4. 2.4 Expansion Interfaces
      1. 2.4.1 Heatsink [ACC] With [J22] Fan Header
      2. 2.4.2 CAN-FD Connector(s) [J4] [J5] [J8] [J9]
      3. 2.4.3 Expansion Header [J27]
      4. 2.4.4 Camera Interface, 22-Pin Flex Connectors [J1] [J2]
      5. 2.4.5 Camera Interface, 40-Pin High Speed [J31] [J30]
      6. 2.4.6 Automation and Control Connector [J17]
  5. 3Circuit Details
    1. 3.1 Top Level Diagram
    2. 3.2 Interface Mapping
    3. 3.3 I2C Address Mapping
    4. 3.4 GPIO Mapping
    5. 3.5 I2C GPIO Expander Mapping
    6. 3.6 Identification EEPROM
  6. 4Revision History

2.4.4 Camera Interface, 22-Pin Flex Connectors [J1] [J2]

The EVM supports two (2) 22-pin flex (0.5mm pitch) connectors [J1][J2] for interfacing with camera modules. Each camera interface provides MIPI CSI-2interface (4Lane), Clock/Control signals, and power (3.3V) to the camera.

To enable camera modules with same addressing to be used simultaneously, I2C mux is used to select each camera. The voltage level for Clock/Control signals is selectable between 1.8V/3.3V.

Table 2-10 Camera 0 Flex Pin Definition [J1]
Pin # Pin Name Description Dir
1 GND Ground Output
2 CSI0_D0_N CSIPort 0 Data Lane 0 Input
3 CSI0_D0_P CSIPort 0 Data Lane 0 Input
4 GND Ground
5 CSI0_D1_N CSIPort 0 Data Lane 1 Input
6 CSI0_D1_P CSIPort 0 Data Lane 1 Input
7 GND Ground
8 CSI0_CLK_N CSIPort 0 CLK Input
9 CSI0_CLK_P CSIPort 0 CLK Input
10 GND Ground
11 CSI0_D2_N CSIPort 0 Data Lane 2 Input
12 CSI0_D2_P CSIPort 0 Data Lane 2 Input
13 GND Ground
14 CSI0_D3_N CSIPort 0 Data Lane 3 Input
15 CSI0_D3_P CSIPort 0 Data Lane 3 Input
16 GND Ground
17 CAM0_PWDN Pwr-Dwn(IO expander) Output
18 CAM0_AUX AUX (WKUP_GPIO0_88) Bi-Dir
19 GND Ground
20 I2C_SCL I2C Clock #1, Mux 0 Output
21 I2C_SDA I2C Data # 1, Mux 0 Bi-Dir
22 Power Power, 3.3V Output
Table 2-11 Camera 1 Flex Pin Definition [J29]
Pin # Pin Name Description Dir
1 GND Ground Output
2 CSI1_D0_N CSIPort 1 Data Lane 0 Input
3 CSI1_D0_P CSIPort 1 Data Lane 0 Input
4 GND Ground
5 CSI1_D1_N CSIPort 1 Data Lane 1 Input
6 CSI1_D1_P CSIPort 1 Data Lane 1 Input
7 GND Ground
8 CSI1_CLK_N CSIPort 1 CLK Input
9 CSI1_CLK_P CSIPort 1 CLK Input
10 GND Ground
11 CSI1_D2_N CSIPort 1 Data Lane 2 Input
12 CSI1_D2_P CSIPort 1 Data Lane 2 Input
13 GND Ground
14 CSI1_D3_N CSIPort 1 Data Lane 3 Input
15 CSI1_D3_P CSIPort 1 Data Lane 3 Input
16 GND Ground
17 CAM1_PWDN Pwr-Dwn(IO expander) Output
18 CAM1_AUX AUX (WKUP_GPIO0_70) Bi-Dir
19 GND Ground
20 I2C_SCL I2C Clock #1, Mux 1 Output
21 I2C_SDA I2C Data # 1, Mux 1 Bi-Dir
22 Power Power, 3.3V Output