SPRUJA3 November   2024 F29H850TU , F29H859TU-Q1 , TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28378D , TMS320F28379D

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F2837x, F2838x, F28P65x and F29H85x
    1. 1.1 F28x to F29x Feature Change Overview
  5. 2C29x Architecture
    1. 2.1 C29x Architecture Overview
      1. 2.1.1 Peripheral Interrupt Priority and Expansion (PIPE)
      2. 2.1.2 Safety and Security Module (SSU)
      3. 2.1.3 Real-Time DMA (RTDMA)
      4. 2.1.4 Lock-step Compare Module (LCM)
    2. 2.2 C28x vs C29x Architecture Overview
  6. 3PCB Design Consideration
    1. 3.1 VSSOSC
    2. 3.2 JTAG
    3. 3.3 VREF
  7. 4Feature Differences for System Consideration
    1. 4.1 New Features in F29H85x
      1. 4.1.1  Analog Subsystem
      2. 4.1.2  Data Logger and Trace (DLT)
      3. 4.1.3  Single Edge Nibble Transmission (SENT)
      4. 4.1.4  Waveform Analyzer Diagnostic (WADI)
      5. 4.1.5  EPWM
      6. 4.1.6  Bootrom
      7. 4.1.7  ERAD
      8. 4.1.8  XBAR
      9. 4.1.9  Error Signaling Module (ESM)
      10. 4.1.10 Error Aggregator
      11. 4.1.11 Hardware Security Module (HSM)
        1. 4.1.11.1 Cryptographic Accelerators
      12. 4.1.12 Safe Interconnect End-to-End (E2E) Safing
      13. 4.1.13 Critical MMR Safing With Parity
      14. 4.1.14 LPOST
    2. 4.2 Communication Module Changes
    3. 4.3 Control Module Changes
    4. 4.4 Analog Module Differences
    5. 4.5 Power Management
      1. 4.5.1 VREGENZ
      2. 4.5.2 Power Consumption
    6. 4.6 Memory Module Changes
    7. 4.7 GPIO Multiplexing Changes
  8. 5Software Development with F29H85x
    1. 5.1 Migration Report Generation Tool
  9. 6References

4 Feature Differences for System Consideration

This section showcases the similarities and differences in features when moving between the F28P65x and F29H85x devices.

Table 4-1 Main Changes in F29H85x
Category Peripheral Information
CPU Subsystem C29x CPU Section 2.1
Memory RAM Section 4.6
FLASH Section 4.6
System Peripheral Interrupt Priority and Expansion (PIPE) Section 2.1.1
Data Logger and Trace (DLT) Section 4.1.2
Real-Time DMA (RTDMA) Section 2.1.3
BOOTROM Section 4.1.6
Enhanced Real-Time Analysis and Diagnostic (ERAD) Section 4.1.7
Crossbar (XBAR) Section 4.1.8
Analog Analog Subsystem Section 4.1.1
Control Enhanced Pulse Width Modulator (EPWM) Section 4.1.5
Communication Single Edge Nibble Transmission (SENT) Section 4.1.3
Safety and Security Waveform Analyzer Diagnostics (WADI) Section 4.1.4
Error Signaling Module (ESM) Section 4.1.9
Safety and Security Module (SSU) Section 2.1.2
Hardware Security Module (HSM) Section 4.1.11
Cryptographic Accelerators Section 4.1.11.1:
  • Symmetric Cryptography
  • Asymmetric Cryptography
  • Hashing Function
Safe Interconnect End-to-End Safing Section 4.1.12
MMR Safing with Parity Section 4.1.13
Logic Power-On Self-Test (LPOST) Section 4.1.14