SPRUJF1C November   2024  – December 2025 AM2612

1.   1
2.   Description
3.   Get Started
4.   Features
5.   5
6. 1Evaluation Module Overview
   1. 1.1 Introduction
      1. 1.1.1 Preface: Read This First
         1. 1.1.1.1 Sitara MCU+ Academy
         2. 1.1.1.2 Important Usage Notes
   2. 1.2 Kit Contents
   3. 1.3 Device Information
      1. 1.3.1 System Architecture Overview
      2. 1.3.2 Component Identification
      3. 1.3.3 Functional Block Diagram
      4. 1.3.4 BoosterPacks
      5. 1.3.5 Device Information
         1. 1.3.5.1 Security
7. 2Hardware
   1. 2.1  Setup
      1. 2.1.1 Standalone Configuration
   2. 2.2  Power Requirements
      1. 2.2.1 Power Input Using USB Type-C Connector
      2. 2.2.2 Power Tree
      3. 2.2.3 Power Status LEDs
   3. 2.3  Header Information
      1. 2.3.1 OSPI Expansion Connector
      2. 2.3.2 ADC/DAC External VREF Headers
      3. 2.3.3 FSI Header
      4. 2.3.4 EQEP Headers
   4. 2.4  Push Buttons
   5. 2.5  Reset
   6. 2.6  Clock
   7. 2.7  Boot Mode Selection
   8. 2.8  GPIO Mapping
   9. 2.9  IO Expander
   10. 2.10 Interfaces
       1. 2.10.1  Memory Interfaces
          1. 2.10.1.1 OSPI
          2. 2.10.1.2 Board ID EEPROM
       2. 2.10.2  Ethernet Interface
          1. 2.10.2.1 Ethernet PHY 0 - RGMII2 / PR0_PRU0
          2. 2.10.2.2 Ethernet PHY 1 - RGMII1 / PR0_PRU1
       3. 2.10.3  I2C
          1. 2.10.3.1 Industrial Application LEDs
       4. 2.10.4  SPI
       5. 2.10.5  UART
       6. 2.10.6  MCAN
       7. 2.10.7  SDFM
       8. 2.10.8  FSI
       9. 2.10.9  JTAG
       10. 2.10.10 Test Automation Pin Mapping
       11. 2.10.11 LIN
       12. 2.10.12 ADC and DAC
       13. 2.10.13 EQEP
       14. 2.10.14 EPWM
       15. 2.10.15 USB
   11. 2.11 BoosterPack Headers
       1. 2.11.1 BoosterPack Mode 00: Standard LaunchPad/BoosterPack Pinout
       2. 2.11.2 BoosterPack Mode 01: Servo Motor Control BoosterPacks Mode
       3. 2.11.3 BoosterPack Mode 10: BOOSTXL-IOLINKM-8 Mode
       4. 2.11.4 BoosterPack Mode 11: C2000 DRVx BoosterPacks Mode
   12. 2.12 Pinmux Mapping
   13. 2.13 Test Points
   14. 2.14 Best Practices
8. 3Software
9. 4Hardware Design Files
10. 5Compliance
11. 6Additional Information
    1. 6.1 Revision E1 Appendix
       1. 6.1.1 TA_POWERDOWNz pulled up by VSYS_TA_3V3 which is powered by VSYS_3V3
       2. 6.1.2 USB2.0_MUX_SEL0 pulled up by R355
       3. 6.1.3 MDIO and MDC of PRU0-ICSS0 needs to be routed to both Ethernet PHYs
       4. 6.1.4 AM261_RGMII1_RXLINK and AM261_RGMII2_RXLINK to be connected to GPIO
    2. 6.2 Revision E2 Appendix
       1. 6.2.1 Revision E2 Changes from E1
       2. 6.2.2 Revision E2 Known Limitations
    3. 6.3 Revision A Appendix
       1. 6.3.1 Revision A Changes from E2
       2. 6.3.2 Revision A Errata
    4.     Trademarks
12. 7References
    1. 7.1 Reference Documents
    2. 7.2 Other TI Components Used in This Design
13. 8Revision History