SPRUJF1C November   2024  – December 2025 AM2612

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
      1. 1.1.1 Preface: Read This First
        1. 1.1.1.1 Sitara MCU+ Academy
        2. 1.1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Device Information
      1. 1.3.1 System Architecture Overview
      2. 1.3.2 Component Identification
      3. 1.3.3 Functional Block Diagram
      4. 1.3.4 BoosterPacks
      5. 1.3.5 Device Information
        1. 1.3.5.1 Security
  7. 2Hardware
    1. 2.1  Setup
      1. 2.1.1 Standalone Configuration
    2. 2.2  Power Requirements
      1. 2.2.1 Power Input Using USB Type-C Connector
      2. 2.2.2 Power Tree
      3. 2.2.3 Power Status LEDs
    3. 2.3  Header Information
      1. 2.3.1 OSPI Expansion Connector
      2. 2.3.2 ADC/DAC External VREF Headers
      3. 2.3.3 FSI Header
      4. 2.3.4 EQEP Headers
    4. 2.4  Push Buttons
    5. 2.5  Reset
    6. 2.6  Clock
    7. 2.7  Boot Mode Selection
    8. 2.8  GPIO Mapping
    9. 2.9  IO Expander
    10. 2.10 Interfaces
      1. 2.10.1  Memory Interfaces
        1. 2.10.1.1 OSPI
        2. 2.10.1.2 Board ID EEPROM
      2. 2.10.2  Ethernet Interface
        1. 2.10.2.1 Ethernet PHY 0 - RGMII2 / PR0_PRU0
        2. 2.10.2.2 Ethernet PHY 1 - RGMII1 / PR0_PRU1
      3. 2.10.3  I2C
        1. 2.10.3.1 Industrial Application LEDs
      4. 2.10.4  SPI
      5. 2.10.5  UART
      6. 2.10.6  MCAN
      7. 2.10.7  SDFM
      8. 2.10.8  FSI
      9. 2.10.9  JTAG
      10. 2.10.10 Test Automation Pin Mapping
      11. 2.10.11 LIN
      12. 2.10.12 ADC and DAC
      13. 2.10.13 EQEP
      14. 2.10.14 EPWM
      15. 2.10.15 USB
    11. 2.11 BoosterPack Headers
      1. 2.11.1 BoosterPack Mode 00: Standard LaunchPad/BoosterPack Pinout
      2. 2.11.2 BoosterPack Mode 01: Servo Motor Control BoosterPacks Mode
      3. 2.11.3 BoosterPack Mode 10: BOOSTXL-IOLINKM-8 Mode
      4. 2.11.4 BoosterPack Mode 11: C2000 DRVx BoosterPacks Mode
    12. 2.12 Pinmux Mapping
    13. 2.13 Test Points
    14. 2.14 Best Practices
  8. 3Software
  9. 4Hardware Design Files
  10. 5Compliance
  11. 6Additional Information
    1. 6.1 Revision E1 Appendix
      1. 6.1.1 TA_POWERDOWNz pulled up by VSYS_TA_3V3 which is powered by VSYS_3V3
      2. 6.1.2 USB2.0_MUX_SEL0 pulled up by R355
      3. 6.1.3 MDIO and MDC of PRU0-ICSS0 needs to be routed to both Ethernet PHYs
      4. 6.1.4 AM261_RGMII1_RXLINK and AM261_RGMII2_RXLINK to be connected to GPIO
    2. 6.2 Revision E2 Appendix
      1. 6.2.1 Revision E2 Changes from E1
      2. 6.2.2 Revision E2 Known Limitations
    3. 6.3 Revision A Appendix
      1. 6.3.1 Revision A Changes from E2
      2. 6.3.2 Revision A Errata
    4.     Trademarks
  12. 7References
    1. 7.1 Reference Documents
    2. 7.2 Other TI Components Used in This Design
  13. 8Revision History

2.12 Pinmux Mapping

The various pinmux options for the BoosterPack connector pins are given below.

Table 2-69 Pinmux Legend
Default signal for BP Header Muxed alternative signalExternal MUX for alternate signal options
Table 2-70 Pinmux Options for J1
Pin#Mode0Mode1Mode2Mode3Mode4Mode5Mode6Mode7Mode8Mode9Mode 10
J1.13V3
J1.2ADC0_AIN1
J1.3PR0_PRU1_GPIO19UART3_RXDPR0_IEP0_EDC_SYNC_OUT0GPMC0_A19GPIO119TRC_CLKEQEP1_AXBAROUT13
MMC0_CMD UART0_TXD LIN0_TXD MCAN0_TX PR1_MDIO0_MDC GPIO78 SDFM1_D0
J1.4PR0_PRU1_GPIO18UART3_TXDPR0_IEP0_EDIO_DATA_IN_OUT31GPMC0_A17GPIO120TRC_CTLEQEP1_BXBAROUT14
J1.5SPI1_CS0EPWM7_AMMC0_D2UART4_TXDPR1_PRU1_GPIO4GPIO15GPMC0_WAIT0ADC_ETCH_XBAROUT4
J1.6ADC2_AIN3
MMC0_CLK UART0_RXD LIN0_RXD MCAN0_RX PR1_MDIO0_MDIO GPIO77 SDFM1_CLK0
J1.7SPI0_CLKPR1_PRU0_GPIO9MMC0_CMDUART3_TXDFSITX0_CLKGPMC0_A7GPIO12ADC_ETCH_XBAROUT1XBAROUT1
PR1_PRU1_GPIO2MII1_COLUART5_TXDGPMC0_AD2GPIO73ADC_ETCH_XBAROUT4
J1.8OSPI0_D0EPWM9_APR1_PRU1_GPIO11UART1_DCDnGPMC0_AD11GPIO3
J1.9I2C0_SCLGPIO135SDFM1_CLK3
J1.10I2C0_SDAGPIO134SDFM1_CLK2
UART2_RTSn EQEP1_INDEX LIN0_TXD UART3_TXD GPIO137 SDFM1_D3
Table 2-71 Pinmux Options for J2
Pin#Mode0Mode1Mode2Mode3Mode4Mode5Mode6Mode7Mode8Mode9Mode10
J2.11MMC0_D2UART2_TXDI2C1_SDAPR1_PRU0_GPIO0GPIO81SDFM1_CLK2
OSPI0_CSn0 SPI0_CLK UART3_TXD UART2_RTSn GPIO1 XBAROUT0
J2.12 PR1_PRU1_GPIO9 MII1_CRS UART5_RXD GPMC0_AD9 GPIO74 ADC_ETCH_XBAROUT5
J2.13EPWM5_BPR1_PRU1_GPIO5OSPI0_RESET_OUT0GPMC0_AD5GPIO54EPWM8_B
J2.14SPI0_D1PR1_PRU0_GPIO1MMC0_D1UART3_RTSnFSITX0_DATA1GPMC0_BE1nGPIO14ADC_ETCH_XBAROUT3XBAROUT3
SPI1_D1EPWM8_BMMC0_CDUART5_RXDOSPI0_RESET_OUT0PR1_PRU1_GPIO15FSIRX0_DATA1GPIO18GPMC0_WPnADC_ETCH_XBAROUT7XBAROUT4
J2.15SPI0_D0PR1_PRU0_GPIO0MMC0_D0UART3_CTSnFSITX0_DATA0GPMC0_A16GPIO13ADC_ETCH_XBAROUT2XBAROUT2
I2C2_SCLPR1_PRU1_GPIO7UART4_RXDGPMC0_AD7GPIO133EQEP0_IDEXSDFM1_D1ADC_ETCH_XBAROUT3
J2.16PORz
J2.17PR0_PRU1_GPIO17PR1_PRU1_GPIO13UART2_RXDPR0_IEP0_EDIO_DATA_IN_OUT30PR1_UART0_TXDUART5_CTSnGPMC0_AD13GPIO125SDFM0_D1
J2.18OSPI0_D1EPWM9_BPR1_PRU1_GPIO12UART1_RInGPMC0_AD12GPIO4
J2.19SPI0_CS0PR1_PRU0_GPIO2MMC0_CLKUART3_RXDGPMC0_A0GPIO11ADC_ETCH_XBAROUT0XBAROUT0
UART2_CTSn PR1_MDIO0_MDC SPI3_CS1 UART5_RXD GPMC0_BE0n_CLE GPIO127 SDFM0_D2 ADC_ETCH_XBAROUT0
PR1_PRU1_GPIO1 UART1_DSRn UART4_CTSn GPMC0_AD1 GPIO72
J2.20GND
Table 2-72 Pinmux Options for J3
Pin#Mode0Mode1Mode2Mode3Mode4Mode5Mode6Mode7Mode8Mode9
J3.215V
J3.22GND
J3.23ADC0_AIN6
J3.24ADC1_AIN0
J3.25ADC2_AIN0
J3.26ADC0_AIN0
J3.27ADC1_AIN4
J3.28ADC2_AIN4
J3.29 ADC0_AIN4
J3.30DAC_OUT
ADC1_AIN6
Table 2-73 Pinmux Options for J4
Pin# Mode0 Mode1 Mode2 Mode3 Mode4 Mode5 Mode6 Mode7 Mode8 Mode9 Mode10 Mode11
J4.31 EPWM8_A PR1_PRU1_GPIO16 OSPI1_D0 MCAN0_RX PR0_PRU1_GPIO7 OSPI0_D0 GPMC0_CSn1 GPIO59 UART4_TXD EPWM8_A
J4.32 EPWM8_B PR1_PRU1_GPIO15 OSPI1_CLK MCAN0_TX OSPI0_CLK GPMC0_AD15 GPIO60 UART4_RXD EPWM9_B
PR0_ECAP0_APWM_OUT PR1_PRU1_GPIO10 UART2_CTSn PR1_ECAP0_APWM_OUT OR1_UART0_RTSn GPMC0_AD10 GPIO123 SDFM0_D0
J4.33 UART1_RXD OSPI0_LBCLKO LIN1_RXD OSPI1_LBCLKO GPMC0_CLK GPIO75
PR1_PRU1_GPIO0 UART1_DSRn UART4_RTSn GPMC0_AD0 GPIO71
J4.34 LIN1_TXD OSPI0_RESET_OUT0 SPI2_CLK PR1_PRU1_GPIO8 OSPI1_RESET_OUT0 UART1_TXD GPMC0_AD8 GPIO20 XBAROUT6 EPWM6_A
J4.35 EPWM4_B PR1_PRU0_GPIO13 GPMC0_A11 GPIO52 EPWM1_B
J4.36 EPWM4_A PR1_PRU0_GPIO12 GPMC0_A10 GPIO51 EPWM4_A
J4.37 EPWM3_B PR1_PRU0_GPIO11 GPMC0_A9 GPIO50 EPWM6_A
J4.38 EPWM3_A PR1_PRU0_GPIO15 GPMC0_A13 GPIO49 EPWM3_A
J4.39 EPWM2_B PR1_PRU0_GPIO16 PR1_PRU0_GPIO7 GPMC0_A14 GPIO48 EPWM2_B
J4.40 EPWM2_A PR1_PRU0_GPIO3 GPMC0_A1 GPIO47 EPWM2_A
Table 2-74 Pinmux Options for J5
Pin#Mode0Mode1Mode2Mode3Mode4Mode5Mode6Mode7Mode8Mode9Mode10
J5.413V3
J5.42ADC1_AIN1
J5.43UART2_RTSnEQEP1_INDEXLIN0_TXDUART3_TXDGPIO137SDFM1_D3
SPI1_CLKEPWM7_BMMC0_D3UART4_RXDPR1_PRU1_GPIO3FSIRX0_CLKGPIO16GPMC0_OEn_REnADC_ETCH_XBAROUT5XBAROUT2
J5.44UART1_RTSnSPI0_CS1LIN0_RXDUART3_RXDGPIO136SDFM1_D2
UART0_RTSnI2C2_SCLSPI3_D0PR1_PRU1_GPIO19PR1_PRU0_GPIO17UART3_RXDGPMC0_WAIT1GPIO25XBAROUT9
J5.45CLKOUT1PR1_PRU0_GPIO7UART2_RTSnPR1_UART0_CTSnGPMC0_A5GPIO122SDFM0_CLK0EQEP1_STROBE
J5.46ADC1_AIN3
J5.47SPI2_CLKPR1_PRU1_GPIO17UART5_TXDGPMC0_WEnGPIO129SDFM0_D3ADC_ETCH_XBAROUT1
J5.48LIN1_RXDOSPI0_ECC_FAILSPI2_CS0PR1_PRU1_GPIO6OSPI1_ECC_FAILUART1_RXDGPMC0_AD6GPIO19OSPI0_RESET_OUT1XBAROUT5EPWM6_B
J5.49I2C1_SCLSPI1_CS0PR1_PRU0_GPIO17GPMC0_WEnGPIO23XBAROUT7
J5.50I2C1_SDASPI3_CLKPR1_PRU0_GPIO18GPMC0_OEn_REnGPIO24XBAROUT8
Table 2-75 Pinmux Options for J6
Pin# Mode0 Mode1 Mode2 Mode3 Mode4 Mode5 Mode6 Mode7 Mode8 Mode9 Mode10 Mode11
J6.51 OSPI0_CSn0 SPI0_CLK UART3_TXD UART2_RTSn GPIO1 XBAROUT0
MMC0_D2 UART2_TXD I2C1_SDA PR1_PRU0_GPIO0 GPIO81 SDFM1_CLK2
J6.52 PR0_PRU1_GPIO7 CPTS0_TS_SYNC PR1_PRU0_GPIO10 PR0_IEP0_EDC_SYNC_OUT1 PR1_UART0_RXD GPMC0_A8 GPIO124 SDFM0_CLK1 SDFM1_D0 UART2_TXD UART5_RTSn
J6.53 OSPI0_D3 SPI0_D1 OSPI0_D4 GPIO6
J6.54 SPI2_D1 PR1_PRU1_GPIO14 UART5_RXD GPMC0_AD14 GPIO128 SDFM0_CLK3 SDFM1_D2 ADC_ETCH_XBAROUT9
J6.55 SPI2_D0 PR1_PRU1_GPIO18 UART4_RTSn PR1_IEP0_ED_SYNC_OUT0 I2C1_SDA MCAN1_RX GPMC0_OEn_REn GPIO130 SDFM1_CLK0
J6.56 PORZ
J6.57 PR1_PRU1_GPIO2 MII1_COL UART5_TXD GPMC0_AD2 GPIO73 ADC_ETCH_XBAROUT4
SPI0_CLK PR1_PRU0_GPIO9 MMC0_CMD UART3_TXD FSITX0_CLK GPMC0_A7 GPIO12 ADC_ETCH_XBAROUT1 XBAROUT1
J6.58 CLKOUT0 LIN1_RXD OSPI0_ECC_FAIL UART1_RXD SPI2_CS0 OSPI1_ECC_FAIL USB0_DRVVBUS GPIO138 SAFETY_ERRORn
J6.59 UART1_CTSn PR1_MDIO0_MDIO SPI2_CS1 PR1_IEP0_EDC_SYNC_OUT1 UART5_CTSn UART5_TXD GPMC0_CLKLB GPIO126 SDFM0_CLK2 SDFM1_D1
J6.60 GND
Table 2-76 Pinmux Options for J7
Pin# Mode0 Mode1 Mode2 Mode3 Mode4 Mode5 Mode6 Mode7 Mode8 Mode9 Mode10
J7.61 5V
J7.62 GND
J7.63 ADC0_AIN2
EPWM1_B PR1_PRU0_GPIO4 GPMC0_A4 GPIO46 EPWM4_B
J7.64 ADC1_AIN2
UART0_CTSn I2C2_SDA SPI3_D1 SPI0_CS1 PR1_PRU0_GPIO7 UART3_TXD GPIO26 XBAROUT10
J7.65 ADC2_AIN2
EPWM0_B PR1_PRU0_GPIO8 GPMC0_A6 GPIO44 EPWM0_B
J7.66 ADC0_AIN5
J7.67 ADC1_AIN5
MMC0_D3 UART3_RTSn PR1_PRU0_GPIO1 GPIO82 SDFM1_D2
J7.68 ADC2_AIN5
MMC0_WP UART0_RTSn I2C2_SCL PR1_PRU0_GPIO2 GPIO83 SDFM1_CLK3
J7.69 DAC_OUT
PR1_PRU1_GPIO0 UART1_DSRn UART4_RTSn GPMC0_AD0 GPIO71
EPWM1_A PR1_PRU0_GPIO6 GPMC0_A4 GPIO45 EPWM1_A
ADC0_AIN3
J7.70 DAC_OUT
PR1_PRU1_GPIO9 MII1_CRS UART5_RXD GPMC0_AD9 GPIO74 ADC_ETCH_XBAROUT5
MMC0_CMD UART0_TXD LIN0_TXD MCAN0_TX PR1_MDIO0_MDC GPIO78 SDFM1_D0
ADC2_AIN6
Table 2-77 Pinmux Options for J8
Pin#Mode0Mode1Mode2Mode3Mode4Mode5Mode6Mode7Mode8Mode9Mode10
J8.71MMC0_D0UART2_RXDI2C1_SCLMCAN1_RXPR1_PRU0_GPIO10GPIO79SDFM1_CLK1
MMC0_D1 MCAN1_TX PR1_PRU0_GPIO9 GPIO80 SDFM1_D1
J8.72SPI2_CS0PR1_PRU0_GPIO19UART4_CTSnPR1_IEP0_EDIO_DATA_IN_OUT31I2C1_SCLMCAN1_TXGPMC0_CSn0GPIO131EQEP0_BSDFM1_D0
PR1_PRU1_GPIO1 MII1_RX_ER UART4_CTSn GPMC0_AD1 GPIO72
J8.73LIN2_RXDUART2_RXDSPI2_D0USB0_DRVVBUSOSPI1_RESET_OUT1OSPI0_RESET_OUT1GPIO21GPMC0_CSn0
J8.74LIN2_TXDUART2_TXDSPI2_D1GPIO22GPMC0_ADVn_ALE
J8.75LIN0_RXDUART1_CTSnI2C0_SDAUART2_TXDGPIO63EPWM7_B
J8.76EPWM7_APR1_PRU1_GPIO4OSPI0_CSn1OSPI1_CSn1GPMC0_AD4GPIO57EPWM7_A
J8.77EPWM6_BPR1_PRU1_GPIO6UART2_RTSnGPMC0_A20GPIO56EPWM6_B
J8.78EPWM6_APR1_PRU1_GPIO8CLKOUT0GPMC0_AD8GPIO55EPWM3_B
J8.79EPWM7_BPR1_PRU1_GPIO3OSPI1_D1OSPI0_D1GPMC0_AD3GPIO58EPWM5_B
J8.80EPWM5_APR1_PRU0_GPIO13GPMC0_A11GPIO52EPWM51_B
Table 2-78 Pinmux Legend
Default signal for BP Header Muxed alternative signalExternal MUX for alternate signal options