SPRUJF7 March   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
      1.      Preface: Read This First
      2. 1.1.1 Sitara MCU+ Academy
      3. 1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Component Identification
      2. 1.3.2 Functional Block Diagram
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1  Additional Images
    2. 2.2  Setup
    3. 2.3  Power Requirements
      1. 2.3.1 Power Tree
      2. 2.3.2 Power Sequence
    4. 2.4  Header Information
      1. 2.4.1 Baseboard Headers (J1, J2, J3)
      2. 2.4.2 HSEC Pinout
      3. 2.4.3 XDS Debug Header (J4)
      4. 2.4.4 FSI Header
      5. 2.4.5 OSPI Expansion Connector
      6. 2.4.6 Ethernet Add-on Board Connector
    5. 2.5  Reset
    6. 2.6  Clock
    7. 2.7  GPIO Mapping
    8. 2.8  Interfaces
      1. 2.8.1 USB
      2. 2.8.2 UART
      3. 2.8.3 FSI
      4. 2.8.4 OSPI
      5. 2.8.5 Ethernet
        1. 2.8.5.1 RGMII
        2. 2.8.5.2 PRU-ICSS
          1. 2.8.5.2.1 On-Board PHY
          2. 2.8.5.2.2 Ethernet Add-on Board
      6. 2.8.6 I2C
      7. 2.8.7 SPI
      8. 2.8.8 TMDSHSECDOCK-AM263 Peripherals
        1. 2.8.8.1 ADC/DAC
        2. 2.8.8.2 MCAN
        3. 2.8.8.3 LIN1
        4. 2.8.8.4 JTAG
        5. 2.8.8.5 GPIO
    9. 2.9  Debug Information
    10. 2.10 Test Points
    11. 2.11 Assembly Instructions
    12. 2.12 Best Practices
  8. 3Software
  9. 4Hardware Design Files
  10. 5Additional Information
    1. 5.1 Trademarks
  11. 6References
    1. 6.1 Other TI Components Used in This Design
  12. 7Revision History

XDS Debug Header (J4)

The XDS debug header (J4) provides debug access to the AM261-SOM-EVM. The XDS debug header is compatible with the XDS110ISO-EVM. Table 2-3 provides a pinout of the J4 header.

CAUTION:

The XDS debug header (J4) is only compatible with the XDS110ISO-EVM. Do not plug in any other debug probe directly into this header. See Section 2.9 for information on using other debug probes with the controlSOM.

Table 2-3 XDS Debug Header (J4) Pinout

EVM Connection

Function

Pin

Pin

Function

EVM Connection

VSYS_3V3_LDO1

IO_TGT_V

1

2

GND

GND

TMS

MCU_TMS

3

4

MCU_TCK

TCK

TDI

MCU_TDI

5

6

MCU_TDO

TDO

GND

GND

7

8

KEY

NC

UART0_RXD

MCU_SCI_RX

9

10

MCU_SCI_TX

UART0_TXD

I2C0_SDA

EE_I2CSDA

11

12

EE_I2CSCL

I2C0_SCL

SPI3_CLK

DAC_SPI_SCLK

13

14

DAC_SPI_PICO

SPI3_D0

SPI3_D1

DAC_SPI_POCI

15

16

DAC_SPI_PTE

SPI3_CS0