SPRZ436G October 2015 – February 2021 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
MMC2 Has PU/PD Contention Immediately after Release from Reset
High
On AM571x SR 1.0 which should always set SYSBOOT15=1, the MMC2_DAT[x] terminals have internal weak pull-down resistors (PD) in the range of 8 kΩ ~ 36 kΩ (1.8 V) or 9 kΩ ~ 82 kΩ (3.3 V) which are turned on by default immediately after the device has been released from reset. The JEDEC eMMC standard requires external weak pull-up resistors (PU) on eMMC CMD and DAT signals, and internal weak pull-up resistors on DAT[7-0] terminals of eMMC devices to prevent inputs from floating. The external resistors are in the range of 4.7 kΩ ~ 100 kΩ and the internal eMMC device resistors are in the range of 10 kΩ ~ 150 kΩ. After reset, these weak pull-up resistors contradict the internal pull state of the device and presents a PU/PD contention on the eMMC DAT signals; this may lead to reliability issues if not handled properly.
On AM571x SR 2.1 and SR 2.0, and AM570x SR 2.1, SR 2.0, the MMC2 DAT[x] terminals have internal weak pull-down resistors (PD) which are disabled by default when SYSBOOT15=0 or enabled by default when SYSBOOT15=1. Refer to the TRM section “Permanent PU/PD disabling” for details.
PU/PD Contention Reliability Issue:
The PU/PD contention applies a mid-supply voltage to the input buffer which may cause excessive current to flow through the input buffer. In this scenario, both FETs (PMOS/NMOS) in the input buffer are partially turned ON, resulting in a current path from VDD through the input buffer to VSS. Total leakage power during this state may be up to 800 µA per input buffer operating at 1.8 V, or up to 2 mA per input buffer operating at 3.3 V. Hysteresis on the input buffers prevents the noise from causing the input logic level to change state, but it does not prevent the current path.
To maintain system reliability, SW should minimize the duration eMMC DAT lines spend in this invalid state.
SW should minimize the time eMMC DAT terminals spend in the PU/PD contention state to a maximum of 200 hours in a device life cycle.
On AM571x SR1.0 (which should always have SYSBOOT15=1) - or AM571x SR 2.1 and SR 2.0/ AM570x SR 2.1 and SR 2.0 when SYSBOOT15=1 - this is done by configuring MMC pinmux configuration to turn off the internal pull-down resistors as early as possible in secondary boot loader (SBL, i.e. the initial software image loaded by the device’s ROM boot loader; one that is responsible for loading subsequent boot images or the main OS). If external pulls are not implemented on the PCB, then the internal PU on eMMC DAT signals should be enabled simultaneously. Alternately, if external pulls are implemented (as recommended by the JEDEC JESD84- B451) the internal pull resistors can be disabled. SW should take care of writing the below values in the listed registers-bit fields:
CTRL_CORE_PAD_GPMC_A24[3:0] = 1 ; mmc2_dat0
CTRL_CORE_PAD_GPMC_A24[16] = 0 ; Enables weak Pull Up/Down
CTRL_CORE_PAD_GPMC_A24[17] = 1 ; Pull Up is selected
CTRL_CORE_PAD_GPMC_A24[18] = 1 ; Receive Mode is Enabled
CTRL_CORE_PAD_GPMC_A24[19] = 0 ; Fast slew is selected
CTRL_CORE_PAD_GPMC_A25[3:0] = 1 ; mmc2_dat1
CTRL_CORE_PAD_GPMC_A25[16] = 0 ; Enables weak Pull Up/Down
CTRL_CORE_PAD_GPMC_A25[17] = 1 ; Pull Up is selected
CTRL_CORE_PAD_GPMC_A25[18] = 1 ; Receive Mode is Enabled
CTRL_CORE_PAD_GPMC_A25[19] = 0 ; Fast slew is selected
CTRL_CORE_PAD_GPMC_A26[3:0] = 1 ; mmc2_dat2
CTRL_CORE_PAD_GPMC_A26[16] = 0 ; Enables weak Pull Up/Down
CTRL_CORE_PAD_GPMC_A26[17] = 1 ; Pull Up is selected
CTRL_CORE_PAD_GPMC_A26[18] = 1 ; Receive Mode is Enabled
CTRL_CORE_PAD_GPMC_A26[19] = 0 ; Fast slew is selected
CTRL_CORE_PAD_GPMC_A27[3:0] = 1 ; mmc2_dat3
CTRL_CORE_PAD_GPMC_A27[16] = 0 ; Enables weak Pull Up/Down
CTRL_CORE_PAD_GPMC_A27[17] = 1 ; Pull Up is selected
CTRL_CORE_PAD_GPMC_A27[18] = 1 ; Receive Mode is Enabled
CTRL_CORE_PAD_GPMC_A27[19] = 0 ; Fast slew is selected
CTRL_CORE_PAD_GPMC_A19[3:0] = 1 ; mmc2_dat4
CTRL_CORE_PAD_GPMC_A19 [16] = 0 ; Enables weak Pull Up/Down
CTRL_CORE_PAD_GPMC_A19 [17] = 1 ; Pull Up is selected
CTRL_CORE_PAD_GPMC_A19 [18] = 1 ; Receive Mode is Enabled
CTRL_CORE_PAD_GPMC_A19 [19] = 0 ; Fast slew is selected
CTRL_CORE_PAD_GPMC_A20[3:0] = 1 ; mmc2_dat5
CTRL_CORE_PAD_GPMC_A20[16] = 0 ; Enables weak Pull Up/Down
CTRL_CORE_PAD_GPMC_A20[17] = 1 ; Pull Up is selected
CTRL_CORE_PAD_GPMC_A20[18] = 1 ; Receive Mode is Enabled
CTRL_CORE_PAD_GPMC_A20[19] = 0 ; Fast slew is selected
CTRL_CORE_PAD_GPMC_A21[3:0] = 1 ; mmc2_dat6
CTRL_CORE_PAD_GPMC_A21[16] = 0 ; Enables weak Pull Up/Down
CTRL_CORE_PAD_GPMC_A21[17] = 1 ; Pull Up is selected
CTRL_CORE_PAD_GPMC_A21[18] = 1 ; Receive Mode is Enabled
CTRL_CORE_PAD_GPMC_A21[19] = 0 ; Fast slew is selected
CTRL_CORE_PAD_GPMC_A22[3:0] = 1 ; mmc2_dat7
CTRL_CORE_PAD_GPMC_A22[16] = 0 ; Enables weak Pull Up/Down
CTRL_CORE_PAD_GPMC_A22[17] = 1 ; Pull Up is selected
CTRL_CORE_PAD_GPMC_A22[18] = 1 ; Receive Mode is Enabled
CTRL_CORE_PAD_GPMC_A22[19] = 0 ; Fast slew is selected
The 200 hours can be distributed any way throughout the lifetime of a device, and can be one instance of 200 hours or any number of occurrences totaling 200 hours.
On AM571x SR 2.1 and SR 2.0 and AM570x SR 2.1 and SR 2.0, if SYSBOOT15=0 then no software workaround is required since the internal pulls are permanently disabled. Note that external pull-up resistors on the MMC data bus are mandatory in this case. It is OK if the software workaround remains since accesses to configure the internal pulls has no effect.
AM571x SR 2.1, 2.0 (if SYSBOOT15=1, as described in i863 above)
AM571x SR 1.0
AM570x SR 2.1, 2.0 (if SYSBOOT15=1, as described in i863 above)
DRA79x: 2.1, 2.0
TDA2Ex (23mm): 2.0, 1.0
TDA2Ex (17mm): 2.1, 2.0
AM571x: 2.1, 2.0, 1.0
AM570x: 2.1, 2.0
DRA72x: 2.0, 1.0
DRA71x: 2.1, 2.0