SPRZ455F December 2020 – February 2025 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
Table 1-1 shows the module(s) that are affected by each usage note.
| MODULE | USAGE NOTE |
|---|---|
| C7x | i2453 — C7x: LBIST MISR changed on SR2.0 |
| USB | i2134 — USB: 2.0 Compliance Receive Sensitivity Test Limitation |
Table 1-2 shows the module(s) that are affected by each advisory.
| MODULE | ADVISORY | SILICON REVISIONS AFFECTED | ||
|---|---|---|---|---|
| SR 1.0 | SR 1.1 | SR 2.0 | ||
| AASRC | i2229 — AASRC: AASRC is not supported | YES | YES | YES |
| ADC | i2151 — ADC: Debounce time control register | NO | YES | YES |
| Boot | i2038 — Boot: FAT16 Fails When Root Block Resides in More Than One Cluster | YES | YES | YES |
| i2081 — Boot: ROM Maximum Timeout per Boot Mode Will Be Half of the Original Value from TRM | YES | NO | NO | |
| i2307 — Boot: ROM does not properly select OSPI clocking modes based on BOOTMODE | YES | YES | YES | |
| i2366 — Boot: ROM does not comprehend specific JEDEC SFDP features for 8D-8D-8D operation | NO | YES | YES | |
| i2371 — Boot: ROM code may hang in UART boot mode during data transfer | YES | YES | YES | |
| i2414 — Boot: Ethernet PHY Scan and Bring-Up Flow doesn't work with PHYs that don't support Auto Negotiation | YES | YES | YES | |
| i2418 — Boot: Secure ROM Panic due to Certificate Info not present | YES | YES | YES | |
| i2422 — Boot: ROM timeout for MMCSD filesystem boot too long | YES | YES | YES | |
| i2435 — Boot: ROM timeout for eMMC boot too long | YES | YES | YES | |
| C66x | i2214 — C66x: Writes to different endpoints can land out of order if not fenced | YES | YES | YES |
| C71x | i2063 — C71x: VCOP Aliasing for CPU Loads and Stores Is Not Supported for Non-Aligned Accesses to the Last Line in the IBUF Buffers | YES | YES | YES |
| i2064 — C71x: DMA Accesses to L1D SRAM May Stall Indefinitely in the Presence Cache Mode Change or Global Writeback in Specific Conditions | YES | YES | YES | |
| i2065 — C71x: The C71x Memory System and CPU May Stall Indefinitely in the Presence L1D Snoops | YES | YES | YES | |
| i2079 — C71x: DMA Accesses to L1D SRAM May Stall Indefinitely in the Presence of CPU Traffic in Specific Conditions | YES | YES | YES | |
| i2087 — C71x: MMA HWA_STATUS Reports Errors Before Application Starts | YES | YES | YES | |
| i2117 — C71x: Register Corruption When MMA HWARCV is in Parallel With Load or Store With uTLB Miss | YES | NO | NO | |
| i2131 — C71x: Memory System May Hang During L2 Writeback Invalidate Operation when L2 Scrubber is Enabled | YES | YES | YES | |
| i2199 — C71x: SE returning incorrect data when non-aligned transposed stream crosses AM1 circular buffer boundary | YES | YES | YES | |
| i2213 — C7x SE: SE Can Hang when a 2 dataphase transaction comes back with differing rstatuses | YES | YES | YES | |
| i2219 — C7x SE: SE Returning incorrect rstatus for uTLB faults | YES | YES | YES | |
| i2271 — C7x SE: SE Can Hang on Page Fault/UMC Error Occurring During SEBRK | YES | YES | YES | |
| i2399 — C7x: CPU NLC Module Not Clearing State on Interrupt | YES | YES | YES | |
| i2454 — C7x: Reset forcing not allowed | YES | YES | NO | |
| CBASS | i2207 — CBASS: Command Arbitration Blocking | YES | YES | YES |
| i2235 — CBASS Null Error Interrupt Not Masked By Enable Register | YES | YES | YES | |
| CC | i2221 — CC: Invasive and Non-Invasive debug enable settings are reset by MCU_RESETz | YES | YES | YES |
| CP | i2283 — Restrictions on how CP Tracer Debug Probes can be used | YES | YES | YES |
| CPTS | i2083 — CPTS: GENF (and ESTF) Reconfiguration Issue | YES | YES | YES |
| i2141 — CPTS: GENF and ESTF Nudge Value Not Cleared by Hardware | YES | YES | YES | |
| CPSW | i2139 — CPSW: ALE Incorrectly Routes Packets With CRC Errors | YES | YES | YES |
| i2148 — CPSW: CPSW Directed Frames are Not Observed When Classification Overrides the Destination Port Via the Egress Opcode Feature | YES | YES | YES | |
| i2184 — CPSW: IET express traffic policing issue | YES | YES | YES | |
| i2185 — CPSW: Policer color marking issue | YES | YES | YES | |
| i2208 — CPSW: ALE IET Express Packet Drops | YES | YES | YES | |
| i2401 — CPSW: Host Timestamps Cause CPSW Port to Lock up | YES | YES | YES | |
| CPSW9G | i2179 — CPSW9G: Reset isolation not working correctly | YES | NO | NO |
| CSI | i2052 — CSI: CSI-Rx to CSI-Tx Retransmit Path Is Unavailable | YES | YES | YES |
| i2190 — CSI: CSI_RX_IF may enter unknown state following an incomplete frame | YES | YES | YES | |
| DDR | i2155 — DDR: Controller DDRSS_CTL_194[9-8] BIST_RESULT Status is Unreliable | YES | YES | YES |
| i2157 — DDR: Controller Anomaly in Setting Wakeup Time for Low Power States | YES | YES | YES | |
| i2159 — DDR: VRCG High Current Mode Must be Used During LPDDR4 CBT | YES | YES | YES | |
| i2160 — DDR: Valid VRef Range Must be Defined During LPDDR4 Command Bus Training | YES | YES | YES | |
| i2166 — DDR: Entry and exit to/from Deep Sleep low-power state can cause PHY internal clock misalignment | YES | YES | YES | |
| i2182 — DDR: Dual-rank non-power-of-2 density not supported with row-cs-bank-col address mapping | YES | YES | YES | |
| i2232 — DDR: Controller postpones more than allowed refreshes after frequency change | YES | YES | YES | |
| i2244 — DDR: Valid stop value must be defined for write DQ VREF training | YES | YES | YES | |
| i2274 — DDR: Including DDR in BSCAN causes current alarm on the DDR supply | YES | YES | YES | |
| DMADVR | i2233 — DMADVR: Link/link_safer sync issue between MAIN and MCU | YES | YES | YES |
| DMSC | i2245 — DMSC: Firewall Region requires specific configuration | YES | YES | YES |
| i2275 — DMSC Secure Boot ROM: Potential Secure Boot vulnerability with explicit EC curve parameters in X.509 certificate | YES | YES | YES | |
| DPHY | i2174 — DPHY: Reset sequence issue can lead to undefined module behavior | YES | NO | NO |
| DRU | i2198 — DRU, UTC: Issue with setting ICNT3 to 0 when not being used | YES | YES | YES |
| i2215 — DRU: TR Submission can be corrupted by C7x writes coming out of order if Non-Atomic TR Submission Mechanism is Used | YES | YES | YES | |
| DSS | i2097 — DSS: Disabling a Layer Connected to Overlay May Result in Synclost During the Next Frame | YES | YES | YES |
| ECC_AGGR | i2049 — ECC_AGGR: Potential IP Clockstop/Reset Sequence Hang due to Pending ECC Aggregator Interrupts | YES | YES | YES |
| i2191 — ECC_AGGR: Erroneous non-correctable parity error assertion for RAM80 | YES | NO | NO | |
| eMMC | i2144 — eMMC: VIO Supply Sequencing | YES | YES | YES |
| FSS | i2048 — FSS: MCU_FSS0_WRT_TYPE Register is Logging Incorrectly | YES | YES | YES |
| GIC | i2101 — GIC: ITS Misbehavior | YES | YES | YES |
| HyperBus | i2119 — HyperBus: HyperBus is Not Functional | YES | NO | NO |
| I3C | i2150 — I3C: SDAPULLEN drives low instead of Hi-Z | YES | YES | YES |
| i2197 — I3C: Slave mode is not supported | YES | YES | YES | |
| i2205 — I3C: Command fetched during pending IBI is not properly processed in some cases | YES | YES | YES | |
| i2216 — I3C: Command execution may fail during slave-initiated IBI address byte reception | YES | YES | YES | |
| IA | i2196 — IA: Potential deadlock scenarios in IA | YES | YES | YES |
| Internal Diagnostics Modules | i2103 — Internal Diagnostics Modules: Incorrect Reporting of ECC_GRP, ECC_BIT and ECC_TYPE Information for Functional Safety Errors | YES | YES | YES |
| ICSSG | i2230 — ICSSG: ICSSG is not supported | YES | YES | YES |
| i2305 — ICSSG: PRU RAM WRT during active FDB lookup write data corruption | YES | YES | YES | |
| JTAG | i2228 — JTAG: TAP used by Debuggers may be inaccessible if TRSTn device pin is never asserted | YES | YES | YES |
| MCAN | i2278 — MCAN: Message Transmit order not guaranteed from dedicated Tx Buffers configured with same Message ID | YES | YES | YES |
| i2279 — MCAN: Specification Update for dedicated Tx Buffers and Tx Queues configured with same Message ID | YES | YES | YES | |
| MCU | i2173 — MCU domain may hang if main domain is issued a reset | YES | NO | NO |
| i2217 — Recommended POST selection via MCU_BOOTMODE[09:08] | YES | YES | NO | |
| MDIO | i2329 — MDIO: MDIO interface corruption (CPSW and PRU-ICSS) | YES | YES | YES |
| MMCSD | i2024 — MMCSD: Peripherals Do Not Support HS400 | YES | YES | YES |
| i2090 — MMCSD: MMCSD1 and MMCSD2 Speed Issue | YES | NO | NO | |
| i2312 — MMCSD: HS200 and SDR104 Command Timeout Window Too Small | YES | YES | YES | |
| MSMC | i2116 — MSMC: Set-hazarding logic withholding RT access waiting on NRT access completion | YES | YES | YES |
| i2149 — MSMC: MSMC Scrubber Only Targets Bottom 16 of 32 Ways of SRAM/L3$ | YES | YES | YES | |
| i2187 — MSMC: Cache Resize to 0 Refreshes Tags instead of Updating them | YES | YES | YES | |
| OSPI | i2115 — OSPI: OSPI Boot Doesn't Support Some xSPI Modes or xSPI Devices | YES | NO | NO |
| i2189 — OSPI: Controller PHY Tuning Algorithm | YES | YES | YES | |
| i2249 — OSPI: Internal PHY Loopback and Internal Pad Loopback clocking modes with DDR timing inoperable | YES | YES | YES | |
| i2351 — OSPI: Controller does not support Continuous Read mode with NAND Flash | YES | YES | YES | |
| i2383 — OSPI: 2-byte address is not supported in PHY DDR mode | YES | YES | YES | |
| PCIe | i2085 — PCIe: Gen2 Capable Endpoint Devices Always Enumerate as Gen1 | YES | YES | YES |
| i2086 — PCIe: MMA Unsupported Request (UR) or Configuration Request Retry Status (CRS) in Configuration Completion Response Packets Results in External Abort | YES | YES | YES | |
| i2094 — PCIe: End of Interrupt (EOI) Not Enabled for PCIe Legacy Interrupts | YES | YES | YES | |
| i2100 — PCIe: Endpoint Destination Select Attribute (ASEL) Based Routing Issue | YES | YES | YES | |
| i2147 — PCIe: Incorrect translation completion type sent by RP for ATS translation request | YES | YES | YES | |
| i2152 — PCIe: Lock up may occur if link down event happens during non-posted command | YES | YES | YES | |
| i2153 — PCIe: Incorrect Reserved Bit Handling in TS1 Packet | YES | YES | YES | |
| i2154 — PCIE: Lane deskew failure during L0s exit | YES | YES | YES | |
| i2183 — PCIe: Link up failure when unused lanes are not assigned to PCIe Controller | YES | YES | YES | |
| i2238 — PCIe: The 2-L SerDes PCIe Reference Clock Output can exceed the 5.0 GT/s Data Rate RMS jitter limit | YES | YES | YES | |
| i2239PCIe: The 2-L SerDes PCIe Reference Clock Output is temporarily disabled while changing Data Rates — | YES | YES | YES | |
| i2246 — PCIe: Automatic compliance entry fails when unused SERDES lanes are not assigned to PCIe Controller | YES | YES | YES | |
| PLL | i2178 — PLL: Corrupted writes to CAL_IN field of PLL12_CAL_CTRL register | YES | YES | YES |
| i2424 — PLL Programming Sequence May Introduce PLL Instability | YES | YES | YES | |
| POK | i2277 — POK: De-Glitch (filter) is based upon only two samples | YES | YES | NO |
| PRG | i2253 — PRG: CTRL_MMR STAT registers are unreliable indicators of POK threshold failure | YES | YES | YES |
| PRU-ICSSG | i2180 — PRU-ICSSG: FDB table corruption during switch operation | YES | NO | NO |
| PSIL | i2137 — PSIL: Clock stop operation can result in undefined behavior | YES | YES | YES |
| i2138 — PSIL: Configuration accesses and source thread teardowns may cause data corruption | YES | YES | YES | |
| R5FSS | i2099 — R5FSS: Deadlock Might Occur When One or More MPU Regions is Configured for Write Allocate Mode | YES | YES | YES |
| i2118 — R5FSS: Debug Access in Lock-Step Mode May Result in Failure | YES | YES | YES | |
| i2129 — R5FSS: High Priority Interrupt is Missed by VIM | YES | YES | YES | |
| i2132 — R5FSS: Interrupt Preemption (Nesting) is Unavailable if Using VIM Vector Interface for Interrupt Handling | YES | YES | YES | |
| i2133 — R5FSS: Lock-Step Mode of Operation is Not Functional | YES | NO | NO | |
| i2161 — Debugger Cannot Access VIM Module While It Is Active | YES | YES | YES | |
| i2162 — R5FSS: The Same Interrupt Cannot be Nested Back-2-Back Within Another Interrupt | YES | YES | YES | |
| i2164 — R5FSS: Errors in ECC injection logic are not detected because the pending interrupts are tied low | YES | YES | YES | |
| i2210 — R5FSS : ATB Flush requests are suppressed | YES | YES | ||
| i2227 — R5FSS: Error interrupt CCM_COMPARE_STAT_PULSE_INTR incorrectly driven | YES | YES | YES | |
| RA | i2054 — RA: Reads from GCFG Region Can Cause Spurious RAM ECC Errors | YES | YES | YES |
| i2095 — RA: Peek to Tail Returns Wrong Data | YES | YES | YES | |
| RAT | i2062 — RAT: Error Interrupt Triggered Even When Error Logging Disable Is Set | YES | YES | YES |
| Reset | i2200 — RESET: TIMEOUT_PER does not work when programmed to 0 value. | YES | YES | YES |
| RINGACC | i2177 — RINGACC: The ring accelerator’s debug transaction trace stream can be corrupted by certain ring access sequences | YES | YES | YES |
| ROM Code | i2306 — ROM Code: Need to turn off internal termination resistors in SERDES | YES | YES | YES |
| SA2_UL | i2098 — SA2_UL: Auth/Decrypt Operations with 2nd Input Thread Does Not Send the DMA Packet Out | YES | YES | YES |
| 2-L SerDes | i2171 — 2-L SerDes: State Change Monitor interrupts are not available | YES | YES | YES |
| SGMII | i2362 — SGMII: Marvell PHY does not ignore the preamble byte resulting in link failure | YES | YES | YES |
| STOG | i2121 — STOG: Flushing Gasket while there is a write transaction in flight can result in dropped write responses | YES | NO | NO |
| i2122 — STOG: Flushing Gasket concurrently with Gasket receiving a write response can cause indefinite non-idleness | YES | YES | YES | |
| i2123 — STOG: Timed Out Emulation Debug write responses from the Slave Gasket always return Success | YES | YES | YES | |
| i2124 — STOG: Read command timeout can result in a gasket hang | YES | NO | NO | |
| i2126 — STOG: Error miscounting when there are two concurrent timeouts or two concurrent unexpected responses | YES | YES | YES | |
| i2127 — STOG: SRC side write data bus hang when a write command timeout occurs the same cycle as last acceptance on DST side | YES | YES | YES | |
| UART | i2096 — UART: Spurious UART Interrupts When Using DMA | YES | YES | YES |
| UDMAP | i2055 — UDMAP: Packet Mode Descriptor Address Space Select Field Restrictions | YES | YES | YES |
| i2143 — UDMAP: TX Channel SA2UL teardown issue | YES | YES | YES | |
| i2146 — UDMA: Force teardown bitfield readback is masked in realtime TX/RX registers | YES | YES | YES | |
| i2163 — UDMAP: UDMA transfers with ICNTs and/or src/dst addr NOT aligned to 64B fail when used in "event trigger" mode | YES | YES | YES | |
| i2168 — UDMAP: Spurious ECC errors due to MAIN/MCU NAVSS rofifo_wr_byten issue | YES | YES | YES | |
| i2320 — UDMA, UDMAP: Descriptors and TRs required to be returned unfragmented | YES | YES | YES | |
| i2234 — UDMA: TR15 hangs if ICNT0 is less than 64 bytes | YES | YES | YES | |
| UFS | i2102 — UFS: Auto-Hibernate can cause false entry/exit errors | YES | YES | YES |
| i2211 — UFS: Hibernate Exit can result in link reinitialization | YES | YES | YES | |
| USART | i2310 — USART: Erroneous clear/trigger of timeout interrupt | YES | YES | YES |
| i2311 — USART: Spurious DMA Interrupts | YES | YES | YES | |
| USB | i2050 — USB: Endpoint OUT Data Queue is Locked Up Due to a Data Packet for an Endpoint that Does Not Have Associated TRB | YES | YES | YES |
| i2067 — USB: Race Condition while Reading TRB from System Memory in Device Mode | YES | YES | YES | |
| i2091 — USB: 2.0 PHY Hangs if Received Signal Amplitude Crosses Squelch Threshold Mmultiple Times Within the Same Packet | YES | YES | YES | |
| i2092 — USB: Invalid Termination of DMA Transfer for Endpoint Following Isochronous Endpoint in SuperSpeed Device Mode | YES | YES | YES | |
| i2093 — USB: DMA Hangs if USB Reset is Received During DMA Transfer in Device Mode | YES | YES | YES | |
| i2134 — USB: 2.0 Compliance Receive Sensitivity Test Limitation | YES | YES | YES | |
| i2409 — USB: USB2 PHY locks up due to short suspend | YES | YES | YES | |
| VPAC | i2188 — VPAC, DMPAC: UTC ECC writeback on queue memory can cause TR corruption | YES | YES | YES |
| VTM | i2053 — VTM: Software Reads from On-Die Temperature Sensors Can Be Corrupted | YES | YES | YES |
| i2128 — VTM: VTM Temperature Monitors (TEMPSENSORs) Should Use a Software Trimming Method | YES | YES | YES | |
| i2145 — VTM: Enabled interrupt event status registers incorrectly return raw unmasked values | YES | YES | YES | |
| xSPI | i2257 — xSPI boot mode redundant image boot failure | NO | YES | YES |