SPRZ455F December 2020 – February 2025 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
C66x: Writes to different endpoints can land out of order if not fenced
The bridge between the C66x and the interrupt aggregator can stall the transaction to clear the event. The trigger for the DRU from C66x goes through a different path, causing a potential race condition where the next event can be generated before the previous event is cleared. When this occurs, software loses an event and will be out of sync with the DRU operation.
A fence operation should be used after the event clear write to ensure that it arrives before the next trigger is sent from the C66x.