SPRZ496E October   2021  – August 2026 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1

 

  1.   1
  2.   TMS320F28003x Real-Time MCUs Silicon ErrataSilicon Revision 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision 0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 0 Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts With Repeat Block
      3. 3.1.3 I2C Slave Mode: Managing Status Flags in Applications with Long Interrupt Response Times
      4. 3.1.4 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision 0 Advisories
      1. 3.2.1  Advisory
      2.      Advisory
      3.      Advisory
      4. 3.2.2  Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10. 3.2.3  Advisory
      11.      Advisory
      12. 3.2.4  Advisory
      13. 3.2.5  Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17. 3.2.6  Advisory
      18.      Advisory
      19. 3.2.7  Advisory
      20. 3.2.8  Advisory
      21.      Advisory
      22. 3.2.9  Advisory
      23.      Advisory
      24. 3.2.10 Advisory
      25. 3.2.11 Advisory
      26.      Advisory
      27.      Advisory
      28.      Advisory
      29.      Advisory
  6. 4Documentation Support
  7. 5Trademarks
  8. 6Revision History

I2C Slave Mode: Managing Status Flags in Applications with Long Interrupt Response Times

Revision Affected: 0

If the application delays servicing of an I2C interrupt while I2C bus activity continues to progress, future bus events can cause multiple status flags in the I2C Status Register (I2CSTR) to become active concurrently. If more than one of these interrupt events is enabled in I2CIER, future interrupts could be lost.

  • This doesn’t apply when operating as an I2C master.
  • This doesn’t apply if each I2CSTR flag is cleared by software before another gets set.

Workaround: Poll the I2CISRC.INTCODE field and execute the corresponding action for each interrupt source until the I2CISRC.INTCODE field has a value of 0 (no interrupt pending).

__interrupt void I2CA_ISR(void){
    uint16_t isrc;
    while((isrc = I2C_getInterruptSource(I2CA_BASE)) != I2C_INTSRC_NONE){
        switch(isrc) {
            case I2C_INTSRC_ARB_LOST: 
                    /* ARBLINT ISR code */ 
                    break;
            case I2C_INTSRC_NO_ACK: 
                    /* NACKINT ISR code */ 
                    break;
            case I2C_INTSRC_REG_ACCESS_RDY: 
                    /* ARDYINT ISR code */ 
                    I2C_clearStatus(I2CA_BASE, I2C_STS_REG_ACCESS_RDY); 
                    break;
            case I2C_INTSRC_RX_DATA_RDY: 
                    /* RRDYINT ISR code, including I2C_getData() call */ 
                    break;
            case I2C_INTSRC_TX_DATA_RDY: 
                    /* XRDYINT ISR code, including I2C_putData() call */ 
                    break;
            case I2C_INTSRC_STOP_CONDITION: 
                    /* SCDINT ISR code */ 
                    break;
            case I2C_INTSRC_ADDR_TARGET: 
                    /* AASINT ISR code */ 
                    break;
        }
        NOP;
        NOP;
    }
    Interrupt_clearACKGroup();
}