SPRZ496E October   2021  – August 2026 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1

 

  1.   1
  2.   TMS320F28003x Real-Time MCUs Silicon ErrataSilicon Revision 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision 0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 0 Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts With Repeat Block
      3. 3.1.3 I2C Slave Mode: Managing Status Flags in Applications with Long Interrupt Response Times
      4. 3.1.4 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision 0 Advisories
      1. 3.2.1  Advisory
      2.      Advisory
      3.      Advisory
      4. 3.2.2  Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10. 3.2.3  Advisory
      11.      Advisory
      12. 3.2.4  Advisory
      13. 3.2.5  Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17. 3.2.6  Advisory
      18.      Advisory
      19. 3.2.7  Advisory
      20. 3.2.8  Advisory
      21.      Advisory
      22. 3.2.9  Advisory
      23.      Advisory
      24. 3.2.10 Advisory
      25. 3.2.11 Advisory
      26.      Advisory
      27.      Advisory
      28.      Advisory
      29.      Advisory
  6. 4Documentation Support
  7. 5Trademarks
  8. 6Revision History

Advisory

C28: Fast Integer Division (FID) and DIVF64 Incorrect Results

Revision Affected

0

Details

Incorrect results can occur for certain 2-cycle FPU instructions when using compiler versions before 22.6.3.LTS or 21.6.2.LTS.

When the below affected 2p FPU Instructions are followed by any of the FID or DIVF64 instructions with less than two delay slots, register corruption can occur which leads to incorrect results.

2-cycle (2p) FPU Instructions which need two delay slots before a FID or DIVF64 instruction:

  • ADDF32
  • SUBF32
  • MPYF32
  • MACF32

Fast Integer Division (FID) instructions:

  • ABSI32DIV32
  • ABSI32DIV32U
  • ABSI64DIV32
  • ABSI64DIV32U
  • ABSI64DIV64
  • ABSI64DIV64U
  • ENEGI32DIV32
  • ENEGI64DIV32
  • ENEGI64DIV64
  • MNEGI32DIV32
  • MNEGI64DIV32
  • MNEGI64DIV64
  • NEGI32DIV32
  • NEGI64DIV32
  • NEGI64DIV64
  • SUBC2UI64
  • SUBC4UI32

DIVF64 instructions:

  • PREDIVF64
  • SUBC3F64
  • POSTDIVF64

Example of issue:

The issue can be reproduced with a sequence like:

ADDF32    R0H, R0H, #32768    ; 2p FPU instruction

NOP                           ; Only one delay slot (insufficient)

ABSI32DIV32 R2H, R1H, R3H     ; Fast Integer Division instruction

In this case, the value in R0H can leak into R1H, causing incorrect results. Adding an additional NOP resolves the issue:

ADDF32    R0H, R0H, #32768    ; 2p FPU instruction

NOP                           ; First delay slot

NOP                           ; Second delay slot (required)

ABSI32DIV32 R2H, R1H, R3H     ; Fast Integer Division instruction

Workarounds

  1. Update to compiler version 22.6.3.LTS, 21.6.2.LTS or later which has fixed this issue.
  2. If using assembly code, ensure two delay slots between affected instruction combinations.