SPRZ569B November   2024  – September 2025 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   F29H85x, F29P58x, and F29P32x MCUs Silicon Errata Silicon Revisions A, 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision B Usage Notes and Advisories
    1. 3.1 Silicon Revision B Usage Notes
    2. 3.2 Silicon Revision B Advisories
      1.      Advisory
      2. 3.2.1  Advisory
      3.      Advisory
      4. 3.2.2  Advisory
      5. 3.2.3  Advisory
      6. 3.2.4  Advisory
      7. 3.2.5  Advisory
      8. 3.2.6  Advisory
      9. 3.2.7  Advisory
      10.      Advisory
      11. 3.2.8  Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15. 3.2.9  Advisory
      16. 3.2.10 Advisory
  6. 4Silicon Revision A Usage Notes and Advisories
    1. 4.1 Silicon Revision A Usage Notes
      1. 4.1.1 Security: New TI Keys Programmed on Silicon Revision B Devices
    2. 4.2 Silicon Revision A Advisories
      1. 4.2.1 Advisory
      2. 4.2.2 Advisory
      3. 4.2.3 Advisory
      4. 4.2.4 Advisory
      5. 4.2.5 Advisory
  7. 5Silicon Revision 0 Usage Notes and Advisories
    1. 5.1 Silicon Revision 0 Usage Notes
    2. 5.2 Silicon Revision 0 Advisories
      1. 5.2.1 Advisory
      2. 5.2.2 Advisory
  8. 6Documentation Support
  9. 7Trademarks
  10. 8Revision History

Advisory

SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields CEVT1SEL, CEVT2SEL, and HZEN Within Three SD-Modulator Clock Cycles can Corrupt SDFM State Machine, Resulting in Spurious Comparator Events

Revisions Affected

0, A, B

Details

Back-to-back writes to SDCPARMx register bit fields CEVT1SEL, CEVT2SEL, and HZEN within three SD-modulator clock cycles can potentially corrupt the SDFM state machine, resulting in spurious comparator events, which can potentially trigger CPU interrupts, ePWM XBAR events, and GPIO output X-BAR events if configured appropriately.

Workaround

Avoid back-to-back writes within three SD-modulator clock cycles or have the SDCPARMx register bit fields configured in one register write.