Details:

R5 access to internal TMU space are also accessing ATC Memory location.

CPU1 access to TMU1 memory map through TCM bus are also initiating accesses to ATCM1 Bank0 RAM (Impacted location are 0x40-0x280) in dual core mode of Cluster configuration.

WR TXN: CORE1 writes to TMU1 is corrupting ATCM1 Bank0 memories contents because valid signal to memory are not blocked

RD TXN: CORE1 reads to TMU1 are not corrupted because of ATC_WAIT being asserted which samples the correct read data from TMU even though ATCM memory accesses are made (No Impact)

Workaround(s):

Use one of the Workarounds:

WA1: Do not use initial 576 bytes (0x40-0x280) of ATCM from CPU1 allocation

WA2: Use CPU0 TMU alone for computation. Don’t use CPU1 TMU