SPRZ578A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
PLL: PLL Programming Sequence Can Introduce PLL Instability
PLL programming sequence has been changed to provide that, if used, all calibration fields are configured prior to enabling the PLL calibration. In addition to the change to the control of the calibration logic, other changes are implemented so that PLL parameters are unchanged while the PLL is enabled.
When in integer mode, the software enables the PLL calibration feature on calibration-capable PLLs. The previous software adjusted calibration modes after CAL_LOCK was asserted. These writes have been observed to cause a loss of PLL lock on some devices. Additionally, even on susceptible devices, the loss of lock is intermittent, but when the loss occurs, dependent circuitry runs at an incorrect frequency; this wrong frequency can show up as slow algorithm execution or communication failures.
Limit on the impact: The calibration logic cannot be used when the PLL is in fractional mode. Therefore, PLLs that are programmed to use fractional mode don't likely see a failure related to the calibration programmation. Nevertheless, because of the change to the full PLL sequence, the new software is recommended for all users.
Do not use clk_pll_16fft_cal_option4() in SYSFW. Provide to use updated PLL programming sequences in SDK v10.0 or later when performing any PLL configuration change.