Details:

The USART may erroneously clear or trigger the timeout interrupt when RHR/MSR/LSR registers are read.

Workaround(s):

For CPU use-case.

• If the timeout interrupt is erroneously cleared:
  • This is Valid since the pending data inside the FIFO retriggers the timeout interrupt
• If timeout interrupt is erroneously set, and the FIFO is empty, use the following SW workaround to clear the interrupt:
  • Set a high value of timeout counter in TIMEOUTH and TIMEOUTL registers
  • Set EFR2 bit 6 to 1 to change timeout mode to periodic
  • Read the IIR register to clear the interrupt
  • Set EFR2 bit 6 back to 0 to change timeout mode back to the original mode

For DMA use-case.

• If timeout interrupt is erroneously cleared:
  • This is valid since the next periodic event retriggers the timeout interrupt
  • User must ensure that RX timeout behavior is in periodic mode by setting EFR2 bit6 to 1
• If timeout interrupt is erroneously set:
  • This causes DMA to be torn down by the SW driver
  • Valid since next incoming data causes SW to setup DMA again