SWAU134 September   2024 CC3301MOD

 

  1.   1
  2.   Description
  3.   Features
  4. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  5. 2Hardware
    1. 2.1 Hardware Features
    2. 2.2 Connector and Jumper Descriptions
      1. 2.2.1 LED Indicators
      2. 2.2.2 Jumper Settings
      3. 2.2.3 BoosterPack Header Assignment
      4. 2.2.4 JTAG Headers
    3. 2.3 Power
      1. 2.3.1 Measure the CC33X1MOD Current Draw
        1. 2.3.1.1 Low Current Measurement (LPDS)
        2. 2.3.1.2 Active Current Measurement
    4. 2.4 Clocking
    5. 2.5 Performing Conducted Testing
  6. 3Implementation Results
    1. 3.1 Evaluation Setups
      1. 3.1.1 MCU and RTOS
      2. 3.1.2 Processor and Linux
      3. 3.1.3 Standalone RF Testing
        1. 3.1.3.1 Radio Tool BP-CC33X1MOD Hardware Setup
  7. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  8. 5Additional Information
    1. 5.1 Trademarks

2.2.3 BoosterPack Header Assignment

The CC33X1MOD BoosterPack™ has two 20-pin header connectors that provide access to many of the CC33X1MOD pins and features. The signal assignment on these connectors is shown in the figure below and described in Table 2-3 and Table 2-4.

Image of the BP-CCC33X1 Pinout and Corresponding SignalsFigure 2-3 CC33X1MOD BoosterPack™ Pinout

Table 2-3 P1 Pin Assignment
PinName (in schematic)Type/Direction for DeviceDescription
P1.1VCC_MCU_3V3InputNo functional purpose
P1.2ReservedN/AN/A
P1.3UART_TX_3V3OutputThe CC33X1MOD UART TX to host for BLE host controller interface
P1.4UART_RX_3V3InputThe CC33X1MOD UART RX from the host for BLE host controller interface
P1.5LP_RESETInputReset line for CC33X1MOD used to enable / disable (active low). Driven by host through LaunchPad pins
P1.6ReservedN/AN/A
P1.7SDIO_CLK_3V3InputSDIO clock or SPI clock. Must be driven by host
P1.8IRQ_WL_3V3OutputInterrupt request from CC33X1MOD to host for Wi-Fi activity
P1.9COEX_GRANT_3V3OutputExternal coexistence interface - grant (reserved for future use)
P1.10ANT_SEL_3V3OutputAntenna select control
P1.21VCC_MCU_5VPower5V supply to board
P1.22GNDGNDBoard ground
P1.23ReservedN/AN/A
P1.24ReservedN/AN/A
P1.25ReservedN/AN/A
P1.26ReservedN/AN/A
P1.27ReservedN/AN/A
P1.28ReservedN/AN/A
P1.29COEX_REQ_3V3InputExternal coexistence interface - request (reserved for future use)
P1.30COEX_PRIORITY_3V3InputExternal coexistence interface - priority (reserved for future use)
Table 2-4 P2 Pin Assignment
PinName (in schematic)Type/Direction for DeviceDescription
P2.11IRQ_BLE_3V3OutputInterrupt request from CC33X1MOD to host for BLE activity
P2.12ReservedN/AN/A
P2.13ReservedN/AN/A
P2.14SDIO_D0_POCI_3V3Input/OutputSDIO data D0 or SPI POCI
P2.15SDIO_CMD_PICO_3V3Input/OutputSDIO command or SPI PICO
P2.16ReservedN/AN/A
P2.17ReservedN/AN/A
P2.18SDIO_D3_3V3 (CS)Input/OutputSDIO data D3 or SPI CS
P2.19SLOW_CLK_IN_3V3InputInput for external RTC clock 32.768kHz
P2.20GNDGNDBoard ground
P2.31ReservedN/AN/A
P2.32ReservedN/AN/A
P2.33ReservedN/AN/A
P2.34LOGGER_3V3OutputTracer from CC33X1MOD (UART TX debug logger)
P2.35ReservedN/AN/A
P2.36UART_RTS_3V3OutputUART RTS from CC33X1MOD to host for BLE HCI flow control
P2.37UART_CTS_3V3InputUART CTS to CC33X1MOD from host for BLE HCI flow control
P2.38SDIO_D1_3V3Input/OutputSDIO data D1
P2.39SDIO_D2_3V3Input/OutputSDIO data D2
P2.40ReservedN/AN/A