SWCU185F january 2018 – march 2023 CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1
Table 20-217 lists the memory-mapped registers for the AUX_SPIM registers. All register offset addresses not listed in Table 20-217 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | SPIMCFG | SPI Master Configuration | SPIMCFG Register (Offset = 0h) [Reset = 00000000h] |
4h | MISOCFG | MISO Configuration | MISOCFG Register (Offset = 4h) [Reset = 00000000h] |
8h | MOSICTL | MOSI Control | MOSICTL Register (Offset = 8h) [Reset = 00000000h] |
Ch | TX8 | Transmit 8 Bit | TX8 Register (Offset = Ch) [Reset = 00000000h] |
10h | TX16 | Transmit 16 Bit | TX16 Register (Offset = 10h) [Reset = 00000000h] |
14h | RX8 | Receive 8 Bit | RX8 Register (Offset = 14h) [Reset = 00000000h] |
18h | RX16 | Receive 16 Bit | RX16 Register (Offset = 18h) [Reset = 00000000h] |
1Ch | SCLKIDLE | SCLK Idle | SCLKIDLE Register (Offset = 1Ch) [Reset = 00000001h] |
20h | DATAIDLE | Data Idle | DATAIDLE Register (Offset = 20h) [Reset = 00000001h] |
Complex bit access types are encoded to fit into small table cells. Table 20-218 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
SPIMCFG is shown in Figure 20-195 and described in Table 20-219.
Return to the Summary Table.
SPI Master Configuration
Write operation stalls until current transfer completes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DIV | PHA | POL | ||||||||||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-2 | DIV | R/W | 0h | SCLK divider. Peripheral clock frequency division gives the SCLK clock frequency. The division factor equals (2 * (DIV+1)): 0x00: Divide by 2. 0x01: Divide by 4. 0x02: Divide by 6. ... 0x3F: Divide by 128. |
1 | PHA | R/W | 0h | Phase of the MOSI and MISO data signals. 0: Sample MISO at leading (odd) edges and shift MOSI at trailing (even) edges of SCLK. 1: Sample MISO at trailing (even) edges and shift MOSI at leading (odd) edges of SCLK. |
0 | POL | R/W | 0h | Polarity of the SCLK signal. 0: SCLK is low when idle, first clock edge rises. 1: SCLK is high when idle, first clock edge falls. |
MISOCFG is shown in Figure 20-196 and described in Table 20-220.
Return to the Summary Table.
MISO Configuration
Write operation stalls until current transfer completes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AUXIO | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4-0 | AUXIO | R/W | 0h | AUXIO to MISO mux. Select the AUXIO pin that connects to MISO. |
MOSICTL is shown in Figure 20-197 and described in Table 20-221.
Return to the Summary Table.
MOSI Control
Write operation stalls until current transfer completes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VALUE | ||||||
R-0h | W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | VALUE | W | 0h | MOSI level control. 0: Set MOSI low. 1: Set MOSI high. |
TX8 is shown in Figure 20-198 and described in Table 20-222.
Return to the Summary Table.
Transmit 8 Bit
Write operation stalls until current transfer completes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DATA | ||||||||||||||||||||||||||||||
R-0h | W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | DATA | W | 0h | 8 bit data transfer. Write DATA to start transfer, MSB first. When transfer completes, MOSI stays at the value of LSB. |
TX16 is shown in Figure 20-199 and described in Table 20-223.
Return to the Summary Table.
Transmit 16 Bit
Write operation stalls until current transfer completes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DATA | ||||||||||||||||||||||||||||||
R-0h | W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | DATA | W | 0h | 16 bit data transfer. Write DATA to start transfer, MSB first. When transfer completes, MOSI stays at the value of LSB. |
RX8 is shown in Figure 20-200 and described in Table 20-224.
Return to the Summary Table.
Receive 8 Bit
Read operation stalls until current transfer completes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DATA | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | DATA | R | 0h | Latest 8 bits received on MISO. |
RX16 is shown in Figure 20-201 and described in Table 20-225.
Return to the Summary Table.
Receive 16 Bit
Read operation stalls until current transfer completes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DATA | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | DATA | R | 0h | Latest 16 bits received on MISO. |
SCLKIDLE is shown in Figure 20-202 and described in Table 20-226.
Return to the Summary Table.
SCLK Idle
Read operation stalls until SCLK is idle with no remaining clock edges.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||
R-0h | R-1h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | STAT | R | 1h | Wait for SCLK idle. Read operation stalls until SCLK is idle with no remaining clock edges. Read then returns 1. AUX_SCE can use this to control CS deassertion. |
DATAIDLE is shown in Figure 20-203 and described in Table 20-227.
Return to the Summary Table.
Data Idle
Read operation stalls until current transfer completes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||
R-0h | R-1h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | STAT | R | 1h | Wait for data idle. Read operation stalls until the SCLK period associated with LSB transmission completes. Read then returns 1. AUX_SCE can use this to control CS deassertion. |