SWCU185F january   2018  – march 2023 CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5. 1.1 Trademarks
  2. 2 Architectural Overview
    1. 2.1 Target Applications
    2. 2.2 Overview
    3. 2.3 Functional Overview
      1. 2.3.1  Arm® Cortex®-M4F
        1. 2.3.1.1 Processor Core
        2. 2.3.1.2 System Timer (SysTick)
        3. 2.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 2.3.1.4 System Control Block
      2. 2.3.2  On-Chip Memory
        1. 2.3.2.1 SRAM
        2. 2.3.2.2 Flash Memory
        3. 2.3.2.3 ROM
      3. 2.3.3  Radio
      4. 2.3.4  Security Core
      5. 2.3.5  General-Purpose Timers
        1. 2.3.5.1 Watchdog Timer
        2. 2.3.5.2 Always-On Domain
      6. 2.3.6  Direct Memory Access
      7. 2.3.7  System Control and Clock
      8. 2.3.8  Serial Communication Peripherals
        1. 2.3.8.1 UART
        2. 2.3.8.2 I2C
        3. 2.3.8.3 I2S
        4. 2.3.8.4 SSI
      9. 2.3.9  Programmable I/Os
      10. 2.3.10 Sensor Controller
      11. 2.3.11 Random Number Generator
      12. 2.3.12 cJTAG and JTAG
      13. 2.3.13 Power Supply System
        1. 2.3.13.1 Supply System
          1. 2.3.13.1.1 VDDS
          2. 2.3.13.1.2 VDDR
          3. 2.3.13.1.3 Digital Core Supply
          4. 2.3.13.1.4 Other Internal Supplies
        2. 2.3.13.2 DC/DC Converter
  3. 3 Arm® Cortex®-M4F Processor
    1. 3.1 Arm® Cortex®-M4F Processor Introduction
    2. 3.2 Block Diagram
    3. 3.3 Overview
      1. 3.3.1 System-Level Interface
      2. 3.3.2 Integrated Configurable Debug
      3. 3.3.3 Trace Port Interface Unit
      4. 3.3.4 Floating Point Unit (FPU)
      5. 3.3.5 Memory Protection Unit (MPU)
      6. 3.3.6 Arm® Cortex®-M4F System Component Details
    4. 3.4 Programming Model
      1. 3.4.1 Processor Mode and Privilege Levels for Software Execution
      2. 3.4.2 Stacks
      3. 3.4.3 Exceptions and Interrupts
      4. 3.4.4 Data Types
    5. 3.5 Arm® Cortex®-M4F Core Registers
      1. 3.5.1 Core Register Map
      2. 3.5.2 Core Register Descriptions
        1. 3.5.2.1  Cortex®General-Purpose Register 0 (R0)
        2. 3.5.2.2  Cortex® General-Purpose Register 1 (R1)
        3. 3.5.2.3  Cortex® General-Purpose Register 2 (R2)
        4. 3.5.2.4  Cortex® General-Purpose Register 3 (R3)
        5. 3.5.2.5  Cortex® General-Purpose Register 4 (R4)
        6. 3.5.2.6  Cortex® General-Purpose Register 5 (R5)
        7. 3.5.2.7  Cortex® General-Purpose Register 6 (R6)
        8. 3.5.2.8  Cortex® General-Purpose Register 7 (R7)
        9. 3.5.2.9  Cortex® General-Purpose Register 8 (R8)
        10. 3.5.2.10 Cortex® General-Purpose Register 9 (R9)
        11. 3.5.2.11 Cortex® General-Purpose Register 10 (R10)
        12. 3.5.2.12 Cortex® General-Purpose Register 11 (R11)
        13. 3.5.2.13 Cortex® General-Purpose Register 12 (R12)
        14. 3.5.2.14 Stack Pointer (SP)
        15. 3.5.2.15 Link Register (LR)
        16. 3.5.2.16 Program Counter (PC)
        17. 3.5.2.17 Program Status Register (PSR)
        18. 3.5.2.18 Priority Mask Register (PRIMASK)
        19. 3.5.2.19 Fault Mask Register (FAULTMASK)
        20. 3.5.2.20 Base Priority Mask Register (BASEPRI)
        21. 3.5.2.21 Control Register (CONTROL)
    6. 3.6 Instruction Set Summary
      1. 3.6.1 Arm® Cortex®-M4F Instructions
      2. 3.6.2 Load and Store Timings
      3. 3.6.3 Binary Compatibility With Other Cortex® Processors
    7. 3.7 Floating Point Unit (FPU)
      1. 3.7.1 About the FPU
      2. 3.7.2 FPU Functional Description
        1. 3.7.2.1 FPU Views of the Register Bank
        2. 3.7.2.2 Modes of Operation
          1. 3.7.2.2.1 Full-Compliance Mode
          2. 3.7.2.2.2 Flush-to-Zero Mode
          3. 3.7.2.2.3 Default NaN Mode
        3. 3.7.2.3 FPU Instruction Set
        4. 3.7.2.4 Compliance With the IEEE 754 Standard
        5. 3.7.2.5 Complete Implementation of the IEEE 754 Standard
        6. 3.7.2.6 IEEE 754 Standard Implementation Choices
          1. 3.7.2.6.1 NaN Handling
          2. 3.7.2.6.2 Comparisons
          3. 3.7.2.6.3 Underflow
        7. 3.7.2.7 Exceptions
      3. 3.7.3 FPU Programmers Model
        1. 3.7.3.1 Enabling the FPU
          1. 3.7.3.1.1 Enabling the FPU
    8. 3.8 Memory Protection Unit (MPU)
      1. 3.8.1 About the MPU
      2. 3.8.2 MPU Functional Description
      3. 3.8.3 MPU Programmers Model
    9. 3.9 Arm® Cortex®-M4F Processor Registers
      1. 3.9.1 CPU_DWT Registers
      2. 3.9.2 CPU_FPB Registers
      3. 3.9.3 CPU_ITM Registers
      4. 3.9.4 CPU_SCS Registers
      5. 3.9.5 CPU_TPIU Registers
  4. 4 Memory Map
    1. 4.1 Memory Map
  5. 5 Arm® Cortex®-M4F Peripherals
    1. 5.1 Arm® Cortex®-M4F Peripherals Introduction
    2. 5.2 Functional Description
      1. 5.2.1 SysTick
      2. 5.2.2 NVIC
        1. 5.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 5.2.2.2 Hardware and Software Control of Interrupts
      3. 5.2.3 SCB
      4. 5.2.4 ITM
      5. 5.2.5 FPB
      6. 5.2.6 TPIU
      7. 5.2.7 DWT
  6. 6 Interrupts and Events
    1. 6.1 Exception Model
      1. 6.1.1 Exception States
      2. 6.1.2 Exception Types
      3. 6.1.3 Exception Handlers
      4. 6.1.4 Vector Table
      5. 6.1.5 Exception Priorities
      6. 6.1.6 Interrupt Priority Grouping
      7. 6.1.7 Exception Entry and Return
        1. 6.1.7.1 Exception Entry
        2. 6.1.7.2 Exception Return
    2. 6.2 Fault Handling
      1. 6.2.1 Fault Types
      2. 6.2.2 Fault Escalation and Hard Faults
      3. 6.2.3 Fault Status Registers and Fault Address Registers
      4. 6.2.4 Lockup
    3. 6.3 Event Fabric
      1. 6.3.1 Introduction
      2. 6.3.2 Event Fabric Overview
        1. 6.3.2.1 Registers
    4. 6.4 AON Event Fabric
      1. 6.4.1 Common Input Event List
      2. 6.4.2 Event Subscribers
        1. 6.4.2.1 Wake-Up Controller (WUC)
        2. 6.4.2.2 Real-Time Clock
        3. 6.4.2.3 MCU Event Fabric
    5. 6.5 MCU Event Fabric
      1. 6.5.1 Common Input Event List
      2. 6.5.2 Event Subscribers
        1. 6.5.2.1 System CPU
        2. 6.5.2.2 NMI
        3. 6.5.2.3 Freeze
    6. 6.6 AON Events
    7. 6.7 Interrupts and Events Registers
      1. 6.7.1 AON_EVENT Registers
      2. 6.7.2 EVENT Registers
  7. 7 JTAG Interface
    1. 7.1  Top-Level Debug System
    2. 7.2  cJTAG
      1. 7.2.1 cJTAG Commands
        1. 7.2.1.1 Mandatory Commands
      2. 7.2.2 Programming Sequences
        1. 7.2.2.1 Opening Command Window
        2. 7.2.2.2 Changing to 4-Pin Mode
        3. 7.2.2.3 Close Command Window
    3. 7.3  ICEPick
      1. 7.3.1 Secondary TAPs
        1. 7.3.1.1 Slave DAP (CPU DAP)
        2. 7.3.1.2 Ordering Slave TAPs and DAPs
      2. 7.3.2 ICEPick Registers
        1. 7.3.2.1 IR Instructions
        2. 7.3.2.2 Data Shift Register
        3. 7.3.2.3 Instruction Register
        4. 7.3.2.4 Bypass Register
        5. 7.3.2.5 Device Identification Register
        6. 7.3.2.6 User Code Register
        7. 7.3.2.7 ICEPick Identification Register
        8. 7.3.2.8 Connect Register
      3. 7.3.3 Router Scan Chain
      4. 7.3.4 TAP Routing Registers
        1. 7.3.4.1 ICEPick Control Block
          1. 7.3.4.1.1 All0s Register
          2. 7.3.4.1.2 ICEPick Control Register
          3. 7.3.4.1.3 Linking Mode Register
        2. 7.3.4.2 Test TAP Linking Block
          1. 7.3.4.2.1 Secondary Test TAP Register
        3. 7.3.4.3 Debug TAP Linking Block
          1. 7.3.4.3.1 Secondary Debug TAP Register
    4. 7.4  ICEMelter
    5. 7.5  Serial Wire Viewer (SWV)
    6. 7.6  Halt In Boot (HIB)
    7. 7.7  Debug and Shutdown
    8. 7.8  Debug Features Supported Through WUC TAP
    9. 7.9  Profiler Register
    10. 7.10 Boundary Scan
  8. 8 Power, Reset, and Clock Management (PRCM)
    1. 8.1 Introduction
    2. 8.2 System CPU Mode
    3. 8.3 Supply System
      1. 8.3.1 Internal DC/DC Converter and Global LDO
    4. 8.4 Digital Power Partitioning
      1. 8.4.1 MCU_VD
        1. 8.4.1.1 MCU_VD Power Domains
      2. 8.4.2 AON_VD
        1. 8.4.2.1 AON_VD Power Domains
    5. 8.5 Clock Management
      1. 8.5.1 System Clocks
        1. 8.5.1.1 Controlling the Oscillators
      2. 8.5.2 Clocks in MCU_VD
        1. 8.5.2.1 Clock Gating
        2. 8.5.2.2 Scaler to GPTs
        3. 8.5.2.3 Scaler to WDT
      3. 8.5.3 Clocks in AON_VD
    6. 8.6 Power Modes
      1. 8.6.1 Start-Up State
      2. 8.6.2 Active Mode
      3. 8.6.3 Idle Mode
      4. 8.6.4 Standby Mode
      5. 8.6.5 Shutdown Mode
    7. 8.7 Reset
      1. 8.7.1 System Resets
        1. 8.7.1.1 Clock Loss Detection
        2. 8.7.1.2 Software-Initiated System Reset
        3. 8.7.1.3 Warm Reset Converted to System Reset
      2. 8.7.2 Reset of the MCU_VD Power Domains and Modules
      3. 8.7.3 Reset of AON_VD
    8. 8.8 PRCM Registers
      1. 8.8.1 DDI_0_OSC Registers
      2. 8.8.2 PRCM Registers
      3. 8.8.3 AON_PMCTL Registers
  9. 9 Versatile Instruction Memory System (VIMS)
    1. 9.1 Introduction
    2. 9.2 VIMS Configurations
      1. 9.2.1 VIMS Modes
        1. 9.2.1.1 GPRAM Mode
        2. 9.2.1.2 Off Mode
        3. 9.2.1.3 Cache Mode
      2. 9.2.2 VIMS FLASH Line Buffers
      3. 9.2.3 VIMS Arbitration
      4. 9.2.4 VIMS Cache TAG Prefetch
    3. 9.3 VIMS Software Remarks
      1. 9.3.1 FLASH Program or Update
      2. 9.3.2 VIMS Retention
        1. 9.3.2.1 Mode 1
        2. 9.3.2.2 Mode 2
        3. 9.3.2.3 Mode 3
    4. 9.4 ROM
    5. 9.5 FLASH
      1. 9.5.1 FLASH Memory Protection
      2. 9.5.2 Memory Programming
      3. 9.5.3 FLASH Memory Programming
      4. 9.5.4 Power Management Requirements
    6. 9.6 ROM Functions
    7. 9.7 VIMS Registers
      1. 9.7.1 FLASH Registers
      2. 9.7.2 VIMS Registers
  10. 10SRAM
    1. 10.1 Introduction
    2. 10.2 Main Features
    3. 10.3 Data Retention
    4. 10.4 Parity and SRAM Error Support
    5. 10.5 SRAM Auto-Initialization
    6. 10.6 Parity Debug Behavior
    7. 10.7 SRAM Registers
      1. 10.7.1 SRAM_MMR Registers
      2. 10.7.2 SRAM Registers
  11. 11Bootloader
    1. 11.1 Bootloader Functionality
      1. 11.1.1 Bootloader Disabling
      2. 11.1.2 Bootloader Backdoor
    2. 11.2 Bootloader Interfaces
      1. 11.2.1 Packet Handling
        1. 11.2.1.1 Packet Acknowledge and Not-Acknowledge Bytes
      2. 11.2.2 Transport Layer
        1. 11.2.2.1 UART Transport
          1. 11.2.2.1.1 UART Baud Rate Automatic Detection
        2. 11.2.2.2 SSI Transport
      3. 11.2.3 Serial Bus Commands
        1. 11.2.3.1  COMMAND_PING
        2. 11.2.3.2  COMMAND_DOWNLOAD
        3. 11.2.3.3  COMMAND_SEND_DATA
        4. 11.2.3.4  COMMAND_SECTOR_ERASE
        5. 11.2.3.5  COMMAND_GET_STATUS
        6. 11.2.3.6  COMMAND_RESET
        7. 11.2.3.7  COMMAND_GET_CHIP_ID
        8. 11.2.3.8  COMMAND_CRC32
        9. 11.2.3.9  COMMAND_BANK_ERASE
        10. 11.2.3.10 COMMAND_MEMORY_READ
        11. 11.2.3.11 COMMAND_MEMORY_WRITE
        12. 11.2.3.12 COMMAND_SET_CCFG
        13. 11.2.3.13 COMMAND_DOWNLOAD_CRC
  12. 12Device Configuration
    1. 12.1 Customer Configuration (CCFG)
    2. 12.2 CCFG Registers
      1. 12.2.1 CCFG Registers
    3. 12.3 Factory Configuration (FCFG)
    4. 12.4 FCFG Registers
      1. 12.4.1 FCFG1 Registers
  13. 13Cryptography
    1. 13.1 AES and Hash Cryptoprocessor Introduction
    2. 13.2 Functional Description
      1. 13.2.1 Debug Capabilities
      2. 13.2.2 Exception Handling
    3. 13.3 Power Management and Sleep Modes
    4. 13.4 Hardware Description
      1. 13.4.1 AHB Slave Bus
      2. 13.4.2 AHB Master Bus
      3. 13.4.3 Interrupts
    5. 13.5 Module Description
      1. 13.5.1 Introduction
      2. 13.5.2 Module Memory Map
      3. 13.5.3 DMA Controller
        1. 13.5.3.1 Internal Operation
        2. 13.5.3.2 Supported DMA Operations
      4. 13.5.4 Master Control and Select Module
        1. 13.5.4.1 Algorithm Select Register
          1. 13.5.4.1.1 Algorithm Select
        2. 13.5.4.2 Master PROT Enable
          1. 13.5.4.2.1 Master PROT-Privileged Access-Enable
        3. 13.5.4.3 Software Reset
      5. 13.5.5 AES Engine
        1. 13.5.5.1 Second Key Registers (Internal, But Clearable)
        2. 13.5.5.2 AES Initialization Vector (IV) Registers
        3. 13.5.5.3 AES I/O Buffer Control, Mode, and Length Registers
        4. 13.5.5.4 Data Input and Output Registers
        5. 13.5.5.5 TAG Registers
      6. 13.5.6 Key Area Registers
        1. 13.5.6.1 Key Write Area Register
        2. 13.5.6.2 Key Written Area Register
        3. 13.5.6.3 Key Size Register
        4. 13.5.6.4 Key Store Read Area Register
        5. 13.5.6.5 Hash Engine
    6. 13.6 AES Module Performance
      1. 13.6.1 Introduction
      2. 13.6.2 Performance for DMA-Based Operations
    7. 13.7 Programming Guidelines
      1. 13.7.1 One-Time Initialization After a Reset
      2. 13.7.2 DMAC and Master Control
        1. 13.7.2.1 Regular Use
        2. 13.7.2.2 Interrupting DMA Transfers
        3. 13.7.2.3 Interrupts, Hardware, and Software Synchronization
      3. 13.7.3 Hashing
        1. 13.7.3.1 Data Format and Byte Order
        2. 13.7.3.2 Basic Hash With Data From DMA
          1. 13.7.3.2.1 New Hash Session With Digest Read Through Slave
          2. 13.7.3.2.2 New Hash Session With Digest to External Memory
          3. 13.7.3.2.3 Resumed Hash Session
        3. 13.7.3.3 HMAC
          1. 13.7.3.3.1 Secure HMAC
        4. 13.7.3.4 Alternative Basic Hash Where Data Originates From Slave Interface
          1. 13.7.3.4.1 New Hash Session
          2. 13.7.3.4.2 Resumed Hash Session
      4. 13.7.4 Encryption and Decryption
        1. 13.7.4.1 Data Format and Byte Order
        2. 13.7.4.2 Key Store
          1. 13.7.4.2.1 Load Keys From External Memory
        3. 13.7.4.3 Basic AES Modes
          1. 13.7.4.3.1 AES-ECB
          2. 13.7.4.3.2 AES-CBC
          3. 13.7.4.3.3 AES-CTR
          4. 13.7.4.3.4 Programming Sequence With DMA Data
        4. 13.7.4.4 CBC-MAC
          1. 13.7.4.4.1 Programming Sequence for CBC-MAC
        5. 13.7.4.5 AES-CCM
          1. 13.7.4.5.1 Programming Sequence for AES-CCM
        6. 13.7.4.6 AES-GCM
          1. 13.7.4.6.1 Programming Sequence for AES-GCM
      5. 13.7.5 Exceptions Handling
        1. 13.7.5.1 Soft Reset
        2. 13.7.5.2 External Port Errors
        3. 13.7.5.3 Key Store Errors
          1. 13.7.5.3.1 PKA Engine
          2. 13.7.5.3.2 Functional Description
            1. 13.7.5.3.2.1 Module Architecture
          3. 13.7.5.3.3 PKA RAM
            1. 13.7.5.3.3.1 PKCP Operations
            2. 13.7.5.3.3.2 Sequencer Operations
              1. 13.7.5.3.3.2.1 Modular Exponentiation Operations
              2. 13.7.5.3.3.2.2 Modular Inversion Operation
              3. 13.7.5.3.3.2.3 Performance
              4. 13.7.5.3.3.2.4 ECC Operations
              5. 13.7.5.3.3.2.5 Performance
              6. 13.7.5.3.3.2.6 ExpMod Performance
              7. 13.7.5.3.3.2.7 Modular Inversion Performance
              8. 13.7.5.3.3.2.8 ECC Operation Performance
            3. 13.7.5.3.3.3 Sequencer ROM Behavior and Interfaces
            4. 13.7.5.3.3.4 Register Configurations
            5. 13.7.5.3.3.5 Operation Sequence
    8. 13.8 Conventions and Compliances
      1. 13.8.1 Conventions Used in This Manual
        1. 13.8.1.1 Terminology
        2. 13.8.1.2 Formulas and Nomenclature
      2. 13.8.2 Compliance
    9. 13.9 Cryptography Registers
      1. 13.9.1 CRYPTO Registers
  14. 14I/O Controller (IOC)
    1. 14.1  Introduction
    2. 14.2  IOC Overview
    3. 14.3  I/O Mapping and Configuration
      1. 14.3.1 Basic I/O Mapping
      2. 14.3.2 Mapping AUXIOs to DIO Pins
      3. 14.3.3 Control External LNA/PA (Range Extender) With I/Os
      4. 14.3.4 Map the 32 kHz System Clock (LF Clock) to DIO
    4. 14.4  Edge Detection on DIO Pins
      1. 14.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT
    5. 14.5  Unused I/O Pins
    6. 14.6  GPIO
    7. 14.7  I/O Pin Capability
    8. 14.8  Peripheral PORTIDs
    9. 14.9  I/O Pins
      1. 14.9.1 Input/Output Modes
        1. 14.9.1.1 Physical Pin
        2. 14.9.1.2 Pin Configuration
    10. 14.10 IOC Registers
      1. 14.10.1 AON_IOC Registers
      2. 14.10.2 GPIO Registers
      3. 14.10.3 IOC Registers
  15. 15Micro Direct Memory Access (µDMA)
    1. 15.1 μDMA Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
    4. 15.4 Initialization and Configuration
      1. 15.4.1 Module Initialization
      2. 15.4.2 Configuring a Memory-to-Memory Transfer
        1. 15.4.2.1 Configure the Channel Attributes
        2. 15.4.2.2 Configure the Channel Control Structure
        3. 15.4.2.3 Start the Transfer
    5. 15.5 µDMA Registers
      1. 15.5.1 UDMA Registers
  16. 16Timers
    1. 16.1 General-Purpose Timers
    2. 16.2 Block Diagram
    3. 16.3 Functional Description
      1. 16.3.1 GPTM Reset Conditions
      2. 16.3.2 Timer Modes
        1. 16.3.2.1 One-Shot or Periodic Timer Mode
        2. 16.3.2.2 Input Edge-Count Mode
        3. 16.3.2.3 Input Edge-Time Mode
        4. 16.3.2.4 PWM Mode
        5. 16.3.2.5 Wait-for-Trigger Mode
      3. 16.3.3 Synchronizing GPT Blocks
      4. 16.3.4 Accessing Concatenated 16- and 32-Bit GPTM Register Values
    4. 16.4 Initialization and Configuration
      1. 16.4.1 One-Shot and Periodic Timer Modes
      2. 16.4.2 Input Edge-Count Mode
      3. 16.4.3 Input Edge-Timing Mode
      4. 16.4.4 PWM Mode
      5. 16.4.5 Producing DMA Trigger Events
    5. 16.5 GPTM Registers
      1. 16.5.1 GPT Registers
  17. 17Real-Time Clock (RTC)
    1. 17.1 Introduction
    2. 17.2 Functional Specifications
      1. 17.2.1 Functional Overview
      2. 17.2.2 Free-Running Counter
      3. 17.2.3 Channels
        1. 17.2.3.1 Capture and Compare
      4. 17.2.4 Events
    3. 17.3 RTC Register Information
      1. 17.3.1 Register Access
      2. 17.3.2 Entering Sleep and Wakeup From Sleep
      3. 17.3.3 AON_RTC:SYNC Register
    4. 17.4 RTC Registers
      1. 17.4.1 AON_RTC Registers
  18. 18Watchdog Timer (WDT)
    1. 18.1 Introduction
    2. 18.2 Functional Description
    3. 18.3 Initialization and Configuration
    4. 18.4 WDT Registers
      1. 18.4.1 WDT Registers
  19. 19True Random Number Generator (TRNG)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 TRNG Software Reset
    4. 19.4 Interrupt Requests
    5. 19.5 TRNG Operation Description
      1. 19.5.1 TRNG Shutdown
      2. 19.5.2 TRNG Alarms
      3. 19.5.3 TRNG Entropy
    6. 19.6 TRNG Low-Level Programing Guide
      1. 19.6.1 Initialization
        1. 19.6.1.1 Interfacing Modules
        2. 19.6.1.2 TRNG Main Sequence
        3. 19.6.1.3 TRNG Operating Modes
          1. 19.6.1.3.1 Polling Mode
          2. 19.6.1.3.2 Interrupt Mode
    7. 19.7 TRNG Registers
      1. 19.7.1 TRNG Registers
  20. 20AUX Domain Sensor Controller and Peripherals
    1. 20.1 Introduction
      1. 20.1.1 AUX Block Diagram
    2. 20.2 Power and Clock Management
      1. 20.2.1 Operational Modes
        1. 20.2.1.1 Dual-Rate AUX Clock
      2. 20.2.2 Use Scenarios
        1. 20.2.2.1 MCU
        2. 20.2.2.2 Sensor Controller
      3. 20.2.3 SCE Clock Emulation
      4. 20.2.4 AUX RAM Retention
    3. 20.3 Sensor Controller
      1. 20.3.1 Sensor Controller Studio
        1. 20.3.1.1 Programming Model
        2. 20.3.1.2 Task Development
        3. 20.3.1.3 Task Testing, Task Debugging and Run-Time Logging
        4. 20.3.1.4 Documentation
      2. 20.3.2 Sensor Controller Engine (SCE)
        1. 20.3.2.1  Registers
          1.        Pipeline Hazards
        2. 20.3.2.2  Memory Architecture
          1.        Memory Access to Instructions and Data
          2.        I/O Access to Module Registers
        3. 20.3.2.3  Program Flow
          1.        Zero-Overhead Loop
        4. 20.3.2.4  Instruction Set
          1. 20.3.2.4.1 Instruction Timing
          2. 20.3.2.4.2 Instruction Prefix
          3. 20.3.2.4.3 Instructions
        5. 20.3.2.5  SCE Event Interface
        6. 20.3.2.6  Math Accelerator (MAC)
        7. 20.3.2.7  Programmable Microsecond Delay
        8. 20.3.2.8  Wake-Up Event Handling
        9. 20.3.2.9  Access to AON Domain Registers
        10. 20.3.2.10 VDDR Recharge
    4. 20.4 Digital Peripheral Modules
      1. 20.4.1 Overview
        1. 20.4.1.1 DDI Control-Configuration
      2. 20.4.2 AIODIO
        1. 20.4.2.1 Introduction
        2. 20.4.2.2 Functional Description
          1. 20.4.2.2.1 Mapping to DIO Pins
          2. 20.4.2.2.2 Configuration
          3. 20.4.2.2.3 GPIO Mode
          4. 20.4.2.2.4 Input Buffer
          5. 20.4.2.2.5 Data Output Source
      3. 20.4.3 SMPH
        1. 20.4.3.1 Introduction
        2. 20.4.3.2 Functional Description
        3. 20.4.3.3 Semaphore Allocation in TI Software
      4. 20.4.4 SPIM
        1. 20.4.4.1 Introduction
        2. 20.4.4.2 Functional Description
          1. 20.4.4.2.1 TX and RX Operations
          2. 20.4.4.2.2 Configuration
          3. 20.4.4.2.3 Timing Diagrams
      5. 20.4.5 Time-to-Digital Converter (TDC)
        1. 20.4.5.1 Introduction
        2. 20.4.5.2 Functional Description
          1. 20.4.5.2.1 Command
          2. 20.4.5.2.2 Conversion Time Configuration
          3. 20.4.5.2.3 Status and Result
          4. 20.4.5.2.4 Clock Source Selection
            1. 20.4.5.2.4.1 Counter Clock
            2. 20.4.5.2.4.2 Reference Clock
          5. 20.4.5.2.5 Start and Stop Events
          6. 20.4.5.2.6 Prescaler
        3. 20.4.5.3 Supported Measurement Types
          1. 20.4.5.3.1 Measure Pulse Width
          2. 20.4.5.3.2 Measure Frequency
          3. 20.4.5.3.3 Measure Time Between Edges of Different Events Sources
            1. 20.4.5.3.3.1 Asynchronous Counter Start – Ignore 0 Stop Events
            2. 20.4.5.3.3.2 Synchronous Counter Start – Ignore 0 Stop Events
            3. 20.4.5.3.3.3 Asynchronous Counter Start – Ignore Stop Events
            4. 20.4.5.3.3.4 Synchronous Counter Start – Ignore Stop Events
          4. 20.4.5.3.4 Pulse Counting
      6. 20.4.6 Timer01
        1. 20.4.6.1 Introduction
        2. 20.4.6.2 Functional Description
      7. 20.4.7 Timer2
        1. 20.4.7.1 Introduction
        2. 20.4.7.2 Functional Description
          1. 20.4.7.2.1 Clock Source
          2. 20.4.7.2.2 Clock Prescaler
          3. 20.4.7.2.3 Counter
          4. 20.4.7.2.4 Event Outputs
          5. 20.4.7.2.5 Channel Actions
            1. 20.4.7.2.5.1 Period and Pulse Width Measurement
              1. 20.4.7.2.5.1.1 Timer Period and Pulse Width Capture
            2. 20.4.7.2.5.2 Clear on Zero, Toggle on Compare Repeatedly
              1. 20.4.7.2.5.2.1 Center-Aligned PWM Generation by Channel 0
            3. 20.4.7.2.5.3 Set on Zero, Toggle on Compare Repeatedly
              1. 20.4.7.2.5.3.1 Edge-Aligned PWM Generation by Channel 0
          6. 20.4.7.2.6 Asynchronous Bus Bridge
    5. 20.5 Analog Peripheral Modules
      1. 20.5.1 Overview
        1. 20.5.1.1 ADI Control-Configuration
        2. 20.5.1.2 Block Diagram
      2. 20.5.2 Analog-to-Digital Converter (ADC)
        1. 20.5.2.1 Introduction
        2. 20.5.2.2 Functional Description
          1. 20.5.2.2.1 Input Selection and Scaling
          2. 20.5.2.2.2 Reference Selection
          3. 20.5.2.2.3 ADC Sample Mode
          4. 20.5.2.2.4 ADC Clock Source
          5. 20.5.2.2.5 ADC Trigger
          6. 20.5.2.2.6 Sample FIFO
          7. 20.5.2.2.7 µDMA Interface
          8. 20.5.2.2.8 Resource Ownership and Usage
      3. 20.5.3 COMPA
        1. 20.5.3.1 Introduction
        2. 20.5.3.2 Functional Description
          1. 20.5.3.2.1 Input Selection
          2. 20.5.3.2.2 Reference Selection
          3. 20.5.3.2.3 LPM Bias and COMPA Enable
          4. 20.5.3.2.4 Resource Ownership and Usage
      4. 20.5.4 COMPB
        1. 20.5.4.1 Introduction
        2. 20.5.4.2 Functional Description
          1. 20.5.4.2.1 Input Selection
          2. 20.5.4.2.2 Reference Selection
          3. 20.5.4.2.3 Resource Ownership and Usage
            1. 20.5.4.2.3.1 Sensor Controller Wakeup
            2. 20.5.4.2.3.2 System CPU Wakeup
      5. 20.5.5 Reference DAC
        1. 20.5.5.1 Introduction
        2. 20.5.5.2 Functional Description
          1. 20.5.5.2.1 Reference Selection
          2. 20.5.5.2.2 Output Voltage Control and Range
          3. 20.5.5.2.3 Sample Clock
            1. 20.5.5.2.3.1 Automatic Phase Control
            2. 20.5.5.2.3.2 Manual Phase Control
            3. 20.5.5.2.3.3 Operational Mode Dependency
          4. 20.5.5.2.4 Output Selection
            1. 20.5.5.2.4.1 Buffer
            2. 20.5.5.2.4.2 External Load
            3. 20.5.5.2.4.3 COMPA_REF
            4. 20.5.5.2.4.4 COMPB_REF
          5. 20.5.5.2.5 LPM Bias
          6. 20.5.5.2.6 Resource Ownership and Usage
      6. 20.5.6 ISRC
        1. 20.5.6.1 Introduction
        2. 20.5.6.2 Functional Description
          1. 20.5.6.2.1 Programmable Current
          2. 20.5.6.2.2 Voltage Reference
          3. 20.5.6.2.3 ISRC Enable
          4. 20.5.6.2.4 Temperature Dependency
          5. 20.5.6.2.5 Resource Ownership and Usage
    6. 20.6 Event Routing and Usage
      1. 20.6.1 AUX Event Bus
        1. 20.6.1.1 Event Signals
        2. 20.6.1.2 Event Subscribers
          1. 20.6.1.2.1 Event Detection
            1. 20.6.1.2.1.1 Detection of Asynchronous Events
            2. 20.6.1.2.1.2 Detection of Synchronous Events
      2. 20.6.2 Event Observation on External Pin
      3. 20.6.3 Events From MCU Domain
      4. 20.6.4 Events to MCU Domain
      5. 20.6.5 Events From AON Domain
      6. 20.6.6 Events to AON Domain
      7. 20.6.7 µDMA Interface
    7. 20.7 Sensor Controller Alias Register Space
    8. 20.8 AUX Domain Sensor Controller and Peripherals Registers
      1. 20.8.1  ADI_4_AUX Registers
      2. 20.8.2  AUX_AIODIO Registers
      3. 20.8.3  AUX_EVCTL Registers
      4. 20.8.4  AUX_SMPH Registers
      5. 20.8.5  AUX_TDC Registers
      6. 20.8.6  AUX_TIMER01 Registers
      7. 20.8.7  AUX_TIMER2 Registers
      8. 20.8.8  AUX_ANAIF Registers
      9. 20.8.9  AUX_SYSIF Registers
      10. 20.8.10 AUX_SPIM Registers
      11. 20.8.11 AUX_MAC Registers
      12. 20.8.12 AUX_SCE Registers
  21. 21Battery Monitor and Temperature Sensor (BATMON)
    1. 21.1 Introduction
    2. 21.2 Functional Description
    3. 21.3 BATMON Registers
      1. 21.3.1 AON_BATMON Registers
  22. 22Universal Asynchronous Receiver/Transmitter (UART)
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Signal Description
    4. 22.4 Functional Description
      1. 22.4.1 Transmit and Receive Logic
      2. 22.4.2 Baud-rate Generation
      3. 22.4.3 Data Transmission
      4. 22.4.4 Modem Handshake Support
        1. 22.4.4.1 Signaling
        2. 22.4.4.2 Flow Control
          1. 22.4.4.2.1 Hardware Flow Control (RTS and CTS)
          2. 22.4.4.2.2 Software Flow Control (Modem Status Interrupts)
      5. 22.4.5 FIFO Operation
      6. 22.4.6 Interrupts
      7. 22.4.7 Loopback Operation
    5. 22.5 Interface to DMA
    6. 22.6 Initialization and Configuration
    7. 22.7 UART Registers
      1. 22.7.1 UART Registers
  23. 23Synchronous Serial Interface (SSI)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 Signal Description
    4. 23.4 Functional Description
      1. 23.4.1 Bit Rate Generation
      2. 23.4.2 FIFO Operation
        1. 23.4.2.1 Transmit FIFO
        2. 23.4.2.2 Receive FIFO
      3. 23.4.3 Interrupts
      4. 23.4.4 Frame Formats
        1. 23.4.4.1 Texas Instruments Synchronous Serial Frame Format
        2. 23.4.4.2 Motorola SPI Frame Format
          1. 23.4.4.2.1 SPO Clock Polarity Bit
          2. 23.4.4.2.2 SPH Phase-Control Bit
        3. 23.4.4.3 Motorola SPI Frame Format With SPO = 0 and SPH = 0
        4. 23.4.4.4 Motorola SPI Frame Format With SPO = 0 and SPH = 1
        5. 23.4.4.5 Motorola SPI Frame Format With SPO = 1 and SPH = 0
        6. 23.4.4.6 Motorola SPI Frame Format With SPO = 1 and SPH = 1
        7. 23.4.4.7 MICROWIRE Frame Format
    5. 23.5 DMA Operation
    6. 23.6 Initialization and Configuration
    7. 23.7 SSI Registers
      1. 23.7.1 SSI Registers
  24. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Introduction
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1 I2C Bus Functional Overview
        1. 24.3.1.1 Start and Stop Conditions
        2. 24.3.1.2 Data Format With 7-Bit Address
        3. 24.3.1.3 Data Validity
        4. 24.3.1.4 Acknowledge
        5. 24.3.1.5 Arbitration
      2. 24.3.2 Available Speed Modes
        1. 24.3.2.1 Standard and Fast Modes
      3. 24.3.3 Interrupts
        1. 24.3.3.1 I2C Master Interrupts
        2. 24.3.3.2 I2C Slave Interrupts
      4. 24.3.4 Loopback Operation
      5. 24.3.5 Command Sequence Flow Charts
        1. 24.3.5.1 I2C Master Command Sequences
        2. 24.3.5.2 I2C Slave Command Sequences
    4. 24.4 Initialization and Configuration
    5. 24.5 I2C Registers
      1. 24.5.1 I2C Registers
  25. 25Inter-IC Sound (I2S)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Signal Description
    4. 25.4 Functional Description
      1. 25.4.1 Dependencies
        1. 25.4.1.1 System CPU Deep-Sleep Mode
      2. 25.4.2 Pin Configuration
      3. 25.4.3 Serial Format Configuration
      4. 25.4.4 I2S
        1. 25.4.4.1 Register Configuration
      5. 25.4.5 Left-Justified (LJF)
        1. 25.4.5.1 Register Configuration
      6. 25.4.6 Right-Justified (RJF)
        1. 25.4.6.1 Register Configuration
      7. 25.4.7 DSP
        1. 25.4.7.1 Register Configuration
      8. 25.4.8 Clock Configuration
        1. 25.4.8.1 Internal Audio Clock Source
        2. 25.4.8.2 External Audio Clock Source
    5. 25.5 Memory Interface
      1. 25.5.1 Sample Word Length
      2. 25.5.2 Channel Mapping
      3. 25.5.3 Sample Storage in Memory
      4. 25.5.4 DMA Operation
        1. 25.5.4.1 Start-Up
        2. 25.5.4.2 Operation
        3. 25.5.4.3 Shutdown
    6. 25.6 Samplestamp Generator
      1. 25.6.1 Samplestamp Counters
      2. 25.6.2 Start-Up Triggers
      3. 25.6.3 Samplestamp Capture
      4. 25.6.4 Achieving Constant Audio Latency
    7. 25.7 Error Detection
    8. 25.8 Usage
      1. 25.8.1 Start-Up Sequence
      2. 25.8.2 Shutdown Sequence
    9. 25.9 I2S Registers
      1. 25.9.1 I2S Registers
  26. 26Radio
    1. 26.1  RF Core
      1. 26.1.1 High-Level Description and Overview
    2. 26.2  Radio Doorbell
      1. 26.2.1 Special Boot Process
      2. 26.2.2 Command and Status Register and Events
      3. 26.2.3 RF Core Interrupts
        1. 26.2.3.1 RF Command and Packet Engine Interrupts
        2. 26.2.3.2 RF Core Hardware Interrupts
        3. 26.2.3.3 RF Core Command Acknowledge Interrupt
      4. 26.2.4 Radio Timer
        1. 26.2.4.1 Compare and Capture Events
        2. 26.2.4.2 Radio Timer Outputs
        3. 26.2.4.3 Synchronization With Real-Time Clock
    3. 26.3  RF Core HAL
      1. 26.3.1 Hardware Support
      2. 26.3.2 Firmware Support
        1. 26.3.2.1 Commands
        2. 26.3.2.2 Command Status
        3. 26.3.2.3 Interrupts
        4. 26.3.2.4 Passing Data
        5. 26.3.2.5 Command Scheduling
          1. 26.3.2.5.1 Triggers
          2. 26.3.2.5.2 Conditional Execution
          3. 26.3.2.5.3 Handling Before Start of Command
        6. 26.3.2.6 Command Data Structures
          1. 26.3.2.6.1 Radio Operation Command Structure
        7. 26.3.2.7 Data Entry Structures
          1. 26.3.2.7.1 Data Entry Queue
          2. 26.3.2.7.2 Data Entry
          3. 26.3.2.7.3 Pointer Entry
          4. 26.3.2.7.4 Partial Read RX Entry
        8. 26.3.2.8 External Signaling
      3. 26.3.3 Command Definitions
        1. 26.3.3.1 Protocol-Independent Radio Operation Commands
          1. 26.3.3.1.1  CMD_NOP: No Operation Command
          2. 26.3.3.1.2  CMD_RADIO_SETUP: Set Up Radio Settings Command
          3. 26.3.3.1.3  CMD_FS_POWERUP: Power Up Frequency Synthesizer
          4. 26.3.3.1.4  CMD_FS_POWERDOWN: Power Down Frequency Synthesizer
          5. 26.3.3.1.5  CMD_FS: Frequency Synthesizer Controls Command
          6. 26.3.3.1.6  CMD_FS_OFF: Turn Off Frequency Synthesizer
          7. 26.3.3.1.7  CMD_RX_TEST: Receiver Test Command
          8. 26.3.3.1.8  CMD_TX_TEST: Transmitter Test Command
          9. 26.3.3.1.9  CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command
          10. 26.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command
          11. 26.3.3.1.11 CMD_COUNT: Counter Command
          12. 26.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation
          13. 26.3.3.1.13 CMD_COUNT_BRANCH: Counter Command With Branch of Command Chain
          14. 26.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern
        2. 26.3.3.2 Protocol-Independent Direct and Immediate Commands
          1. 26.3.3.2.1  CMD_ABORT: ABORT Command
          2. 26.3.3.2.2  CMD_STOP: Stop Command
          3. 26.3.3.2.3  CMD_GET_RSSI: Read RSSI Command
          4. 26.3.3.2.4  CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command
          5. 26.3.3.2.5  CMD_TRIGGER: Generate Command Trigger
          6. 26.3.3.2.6  CMD_GET_FW_INFO: Request Information on the Firmware Being Run
          7. 26.3.3.2.7  CMD_START_RAT: Asynchronously Start Radio Timer Command
          8. 26.3.3.2.8  CMD_PING: Respond With Interrupt
          9. 26.3.3.2.9  CMD_READ_RFREG: Read RF Core Register
          10. 26.3.3.2.10 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode
          11. 26.3.3.2.11 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode
          12. 26.3.3.2.12 CMD_DISABLE_RAT_CH: Disable RAT Channel
          13. 26.3.3.2.13 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode
          14. 26.3.3.2.14 CMD_ARM_RAT_CH: Arm RAT Channel
          15. 26.3.3.2.15 CMD_DISARM_RAT_CH: Disarm RAT Channel
          16. 26.3.3.2.16 CMD_SET_TX_POWER: Set Transmit Power
          17. 26.3.3.2.17 CMD_SET_TX20_POWER: Set Transmit Power of the 20 dBm PA
          18. 26.3.3.2.18 CMD_UPDATE_FS: Set New Synthesizer Frequency Without Recalibration (Depricated)
          19. 26.3.3.2.19 CMD_MODIFY_FS: Set New Synthesizer Frequency Without Recalibration
          20. 26.3.3.2.20 CMD_BUS_REQUEST: Request System BUS Available for RF Core
      4. 26.3.4 Immediate Commands for Data Queue Manipulation
        1. 26.3.4.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue
        2. 26.3.4.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry From Queue
        3. 26.3.4.3 CMD_FLUSH_QUEUE: Flush Queue
        4. 26.3.4.4 CMD_CLEAR_RX: Clear All RX Queue Entries
        5. 26.3.4.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries From Queue
    4. 26.4  Data Queue Usage
      1. 26.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
        1. 26.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading
        2. 26.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry
        3. 26.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue
        4. 26.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data
        5. 26.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry
      2. 26.4.2 Radio CPU Usage Model
        1. 26.4.2.1 Receive Queues
        2. 26.4.2.2 Transmit Queues
    5. 26.5  IEEE 802.15.4
      1. 26.5.1 IEEE 802.15.4 Commands
        1. 26.5.1.1 IEEE 802.15.4 Radio Operation Command Structures
        2. 26.5.1.2 IEEE 802.15.4 Immediate Command Structures
        3. 26.5.1.3 Output Structures
        4. 26.5.1.4 Other Structures and Bit Fields
      2. 26.5.2 Interrupts
      3. 26.5.3 Data Handling
        1. 26.5.3.1 Receive Buffers
        2. 26.5.3.2 Transmit Buffers
      4. 26.5.4 Radio Operation Commands
        1. 26.5.4.1 RX Operation
          1. 26.5.4.1.1 Frame Filtering and Source Matching
            1. 26.5.4.1.1.1 Frame Filtering
            2. 26.5.4.1.1.2 Source Matching
          2. 26.5.4.1.2 Frame Reception
          3. 26.5.4.1.3 ACK Transmission
          4. 26.5.4.1.4 End of Receive Operation
          5. 26.5.4.1.5 CCA Monitoring
        2. 26.5.4.2 Energy Detect Scan Operation
        3. 26.5.4.3 CSMA-CA Operation
        4. 26.5.4.4 Transmit Operation
        5. 26.5.4.5 Receive Acknowledgment Operation
        6. 26.5.4.6 Abort Background-Level Operation Command
      5. 26.5.5 Immediate Commands
        1. 26.5.5.1 Modify CCA Parameter Command
        2. 26.5.5.2 Modify Frame-Filtering Parameter Command
        3. 26.5.5.3 Enable or Disable Source Matching Entry Command
        4. 26.5.5.4 Abort Foreground-Level Operation Command
        5. 26.5.5.5 Stop Foreground-Level Operation Command
        6. 26.5.5.6 Request CCA and RSSI Information Command
    6. 26.6  Bluetooth® low energy
      1. 26.6.1 Bluetooth® low energy Commands
        1. 26.6.1.1 Command Data Definitions
          1. 26.6.1.1.1 Bluetooth® low energy Command Structures
        2. 26.6.1.2 Parameter Structures
        3. 26.6.1.3 Output Structures
        4. 26.6.1.4 Other Structures and Bit Fields
      2. 26.6.2 Interrupts
    7. 26.7  Data Handling
      1. 26.7.1 Receive Buffers
      2. 26.7.2 Transmit Buffers
    8. 26.8  Radio Operation Command Descriptions
      1. 26.8.1  Bluetooth® 5 Radio Setup Command
      2. 26.8.2  Radio Operation Commands for Bluetooth® low energy Packet Transfer
      3. 26.8.3  Coding Selection for Coded PHY
      4. 26.8.4  Parameter Override
      5. 26.8.5  Link Layer Connection
      6. 26.8.6  Slave Command
      7. 26.8.7  Master Command
      8. 26.8.8  Legacy Advertiser
        1. 26.8.8.1 Connectable Undirected Advertiser Command
        2. 26.8.8.2 Connectable Directed Advertiser Command
        3. 26.8.8.3 Nonconnectable Advertiser Command
        4. 26.8.8.4 Scannable Undirected Advertiser Command
      9. 26.8.9  Bluetooth® 5 Advertiser Commands
        1. 26.8.9.1 Common Extended Advertising Packets
        2. 26.8.9.2 Extended Advertiser Command
        3. 26.8.9.3 Secondary Channel Advertiser Command
      10. 26.8.10 Scanner Commands
        1. 26.8.10.1 Scanner Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.10.2 Scanner Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.10.3 Scanner Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.10.4 ADI Filtering
        5. 26.8.10.5 End of Scanner Commands
      11. 26.8.11 Initiator Command
        1. 26.8.11.1 Initiator Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.11.2 Initiator Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.11.3 Initiator Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.11.4 Automatic Window Offset Insertion
        5. 26.8.11.5 End of Initiator Commands
      12. 26.8.12 Generic Receiver Command
      13. 26.8.13 PHY Test Transmit Command
      14. 26.8.14 Whitelist Processing
      15. 26.8.15 Backoff Procedure
      16. 26.8.16 AUX Pointer Processing
      17. 26.8.17 Dynamic Change of Device Address
    9. 26.9  Immediate Commands
      1. 26.9.1 Update Advertising Payload Command
    10. 26.10 Proprietary Radio
      1. 26.10.1 Packet Formats
      2. 26.10.2 Commands
        1. 26.10.2.1 Command Data Definitions
          1. 26.10.2.1.1 Command Structures
        2. 26.10.2.2 Output Structures
        3. 26.10.2.3 Other Structures and Bit Fields
      3. 26.10.3 Interrupts
      4. 26.10.4 Data Handling
        1. 26.10.4.1 Receive Buffers
        2. 26.10.4.2 Transmit Buffers
      5. 26.10.5 Radio Operation Command Descriptions
        1. 26.10.5.1 End of Operation
        2. 26.10.5.2 Proprietary Mode Setup Command
          1. 26.10.5.2.1 IEEE 802.15.4g Packet Format
        3. 26.10.5.3 Transmitter Commands
          1. 26.10.5.3.1 Standard Transmit Command, CMD_PROP_TX
          2. 26.10.5.3.2 Advanced Transmit Command, CMD_PROP_TX_ADV
        4. 26.10.5.4 Receiver Commands
          1. 26.10.5.4.1 Standard Receive Command, CMD_PROP_RX
          2. 26.10.5.4.2 Advanced Receive Command, CMD_PROP_RX_ADV
        5. 26.10.5.5 Carrier-Sense Operation
          1. 26.10.5.5.1 Common Carrier-Sense Description
          2. 26.10.5.5.2 Carrier-Sense Command, CMD_PROP_CS
          3. 26.10.5.5.3 Sniff Mode Receiver Commands, CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF
      6. 26.10.6 Immediate Commands
        1. 26.10.6.1 Set Packet Length Command, CMD_PROP_SET_LEN
        2. 26.10.6.2 Restart Packet RX Command, CMD_PROP_RESTART_RX
    11. 26.11 Radio Registers
      1. 26.11.1 RFC_RAT Registers
      2. 26.11.2 RFC_DBELL Registers
      3. 26.11.3 RFC_PWR Registers
  27. 27Revision History

20.8.9 AUX_SYSIF Registers

Table 20-174 lists the memory-mapped registers for the AUX_SYSIF registers. All register offset addresses not listed in Table 20-174 should be considered as reserved locations and the register contents should not be modified.

Table 20-174 AUX_SYSIF Registers
OffsetAcronymRegister NameSection
0hOPMODEREQOperational Mode RequestOPMODEREQ Register (Offset = 0h) [Reset = 00000000h]
4hOPMODEACKOperational Mode AcknowledgementOPMODEACK Register (Offset = 4h) [Reset = 00000000h]
8hPROGWU0CFGProgrammable Wakeup 0 ConfigurationPROGWU0CFG Register (Offset = 8h) [Reset = 00000000h]
ChPROGWU1CFGProgrammable Wakeup 1 ConfigurationPROGWU1CFG Register (Offset = Ch) [Reset = 00000000h]
10hPROGWU2CFGProgrammable Wakeup 2 ConfigurationPROGWU2CFG Register (Offset = 10h) [Reset = 00000000h]
14hPROGWU3CFGProgrammable Wakeup 3 ConfigurationPROGWU3CFG Register (Offset = 14h) [Reset = 00000000h]
18hSWWUTRIGSoftware Wakeup TriggersSWWUTRIG Register (Offset = 18h) [Reset = 00000000h]
1ChWUFLAGSWakeup FlagsWUFLAGS Register (Offset = 1Ch) [Reset = 00000000h]
20hWUFLAGSCLRWakeup Flags ClearWUFLAGSCLR Register (Offset = 20h) [Reset = 0000000Fh]
24hWUGATEWakeup GateWUGATE Register (Offset = 24h) [Reset = 00000000h]
28hVECCFG0Vector Configuration 0VECCFG0 Register (Offset = 28h) [Reset = 00000000h]
2ChVECCFG1Vector Configuration 1VECCFG1 Register (Offset = 2Ch) [Reset = 00000000h]
30hVECCFG2Vector Configuration 2VECCFG2 Register (Offset = 30h) [Reset = 00000000h]
34hVECCFG3Vector Configuration 3VECCFG3 Register (Offset = 34h) [Reset = 00000000h]
38hVECCFG4Vector Configuration 4VECCFG4 Register (Offset = 38h) [Reset = 00000000h]
3ChVECCFG5Vector Configuration 5VECCFG5 Register (Offset = 3Ch) [Reset = 00000000h]
40hVECCFG6Vector Configuration 6VECCFG6 Register (Offset = 40h) [Reset = 00000000h]
44hVECCFG7Vector Configuration 7VECCFG7 Register (Offset = 44h) [Reset = 00000000h]
48hEVSYNCRATEEvent Synchronization RateEVSYNCRATE Register (Offset = 48h) [Reset = 00000000h]
4ChPEROPRATEPeripheral Operational RatePEROPRATE Register (Offset = 4Ch) [Reset = 00000000h]
50hADCCLKCTLADC Clock ControlADCCLKCTL Register (Offset = 50h) [Reset = 00000000h]
54hTDCCLKCTLTDC Counter Clock ControlTDCCLKCTL Register (Offset = 54h) [Reset = 00000000h]
58hTDCREFCLKCTLTDC Reference Clock ControlTDCREFCLKCTL Register (Offset = 58h) [Reset = 00000000h]
5ChTIMER2CLKCTLAUX_TIMER2 Clock ControlTIMER2CLKCTL Register (Offset = 5Ch) [Reset = 00000000h]
60hTIMER2CLKSTATAUX_TIMER2 Clock StatusTIMER2CLKSTAT Register (Offset = 60h) [Reset = 00000000h]
64hTIMER2CLKSWITCHAUX_TIMER2 Clock SwitchTIMER2CLKSWITCH Register (Offset = 64h) [Reset = 00000001h]
68hTIMER2DBGCTLAUX_TIMER2 Debug ControlTIMER2DBGCTL Register (Offset = 68h) [Reset = 00000000h]
70hCLKSHIFTDETClock Shift DetectionCLKSHIFTDET Register (Offset = 70h) [Reset = 00000001h]
74hRECHARGETRIGVDDR Recharge TriggerRECHARGETRIG Register (Offset = 74h) [Reset = 00000000h]
78hRECHARGEDETVDDR Recharge DetectionRECHARGEDET Register (Offset = 78h) [Reset = 00000000h]
7ChRTCSUBSECINC0Real Time Counter Sub Second Increment 0RTCSUBSECINC0 Register (Offset = 7Ch) [Reset = 00000000h]
80hRTCSUBSECINC1Real Time Counter Sub Second Increment 1RTCSUBSECINC1 Register (Offset = 80h) [Reset = 00000000h]
84hRTCSUBSECINCCTLReal Time Counter Sub Second Increment ControlRTCSUBSECINCCTL Register (Offset = 84h) [Reset = 00000000h]
88hRTCSECReal Time Counter SecondRTCSEC Register (Offset = 88h) [Reset = 00000000h]
8ChRTCSUBSECReal Time Counter Sub-SecondRTCSUBSEC Register (Offset = 8Ch) [Reset = 00000000h]
90hRTCEVCLRAON_RTC Event ClearRTCEVCLR Register (Offset = 90h) [Reset = 00000000h]
94hBATMONBATAON_BATMON Battery Voltage ValueBATMONBAT Register (Offset = 94h) [Reset = 00000000h]
9ChBATMONTEMPAON_BATMON Temperature ValueBATMONTEMP Register (Offset = 9Ch) [Reset = 00000000h]
A0hTIMERHALTTimer HaltTIMERHALT Register (Offset = A0h) [Reset = 00000000h]
B0hTIMER2BRIDGEAUX_TIMER2 BridgeTIMER2BRIDGE Register (Offset = B0h) [Reset = 00000000h]
B4hSWPWRPROFSoftware Power ProfilerSWPWRPROF Register (Offset = B4h) [Reset = 00000000h]

Complex bit access types are encoded to fit into small table cells. Table 20-175 shows the codes that are used for access types in this section.

Table 20-175 AUX_SYSIF Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
RHR
H		Read
Set or cleared by hardware
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

20.8.9.1 OPMODEREQ Register (Offset = 0h) [Reset = 00000000h]

OPMODEREQ is shown in Figure 20-154 and described in Table 20-176.

Return to the Summary Table.

Operational Mode Request
AUX can operate in three operational modes. Each mode is associated with:
- a SCE clock source or rate, given by AON_PMCTL:AUXSCECLK. This rate is termed SCE_RATE.
- a system power supply state request. AUX can request powerdown (uLDO) or active (GLDO or DCDC) system power supply state.
- a specific system response to an active AUX wakeup flag. The response is dependent on what operational mode is requested.
uLDO power supply state offers limited current supply. AUX_SCE cannot use certain peripherals and functions such as AUX_DDI0_OSC, AUX_TDC and AUX_ANAIF ADC interface in this power supply state.
Follow these rules:
- It is not allowed to change a request until it has been acknowledged through OPMODEACK.
- A change in mode request must happen stepwise along this sequence, the direction is irrelevant:
PDA - A - LP - PDLP.
Failure to follow these rules might result in unexpected behavior and must be avoided.

Figure 20-154 OPMODEREQ Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDREQ
R-0hR/W-0h
Table 20-176 OPMODEREQ Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0REQR/W0hAUX operational mode request.
0h = Active operational mode, characterized by:
- Active system power supply state (GLDO or DCDC) request.
- AON_PMCTL:AUXSCECLK.SRC sets the SCE clock frequency (SCE_RATE).
- An active wakeup flag does not change operational mode.
1h = Lowpower operational mode, characterized by:
- Powerdown system power supply state (uLDO) request.
- SCE clock frequency (SCE_RATE) equals SCLK_MF.
- An active wakeup flag does not change operational mode.
2h = Powerdown operational mode with wakeup to active mode, characterized by:
- Powerdown system power supply state (uLDO) request.
- AON_PMCTL:AUXSCECLK.PD_SRC sets the SCE clock frequency (SCE_RATE).
- An active wakeup flag overrides the operational mode externally to active (A) as long as the flag is set.
3h = Powerdown operational mode with wakeup to lowpower mode, characterized by:
- Powerdown system power supply state (uLDO) request.
- AON_PMCTL:AUXSCECLK.PD_SRC sets the SCE clock frequency (SCE_RATE).
- An active wakeup flag overrides the operational mode externally to lowpower (LP) as long as the flag is set.

20.8.9.2 OPMODEACK Register (Offset = 4h) [Reset = 00000000h]

OPMODEACK is shown in Figure 20-155 and described in Table 20-177.

Return to the Summary Table.

Operational Mode Acknowledgement
AUX_SCE program must assume that the current operational mode is the one acknowledged.

Figure 20-155 OPMODEACK Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDACK
R-0hR-0h
Table 20-177 OPMODEACK Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0ACKR0hAUX operational mode acknowledgement.
0h = Active operational mode is acknowledged.
1h = Lowpower operational mode is acknowledged.
2h = Powerdown operational mode with wakeup to active mode is acknowledged.
3h = Powerdown operational mode with wakeup to lowpower mode is acknowledged.

20.8.9.3 PROGWU0CFG Register (Offset = 8h) [Reset = 00000000h]

PROGWU0CFG is shown in Figure 20-156 and described in Table 20-178.

Return to the Summary Table.

Programmable Wakeup 0 Configuration
Configure this register to enable a customized AUX wakeup flag. The wakeup flag will be captured by AON_PMCTL which responds according to the current operational mode. You can select WUFLAGS.PROG_WU0 to trigger execution of a programmable AUX_SCE vector by configuration of VECCFGn. You need to follow the procedure described in WUFLAGSCLR to clear this flag. You need to follow the procedure described in WUGATE to configure it.

Figure 20-156 PROGWU0CFG Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDPOLENWU_SRC
R-0hR/W-0hR/W-0hR/W-0h
Table 20-178 PROGWU0CFG Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7POLR/W0hPolarity of WU_SRC.
The procedure used to clear the wakeup flag decides level or edge sensitivity, see WUFLAGSCLR.PROG_WU0.
0h = The wakeup flag is set when WU_SRC is high or goes high.
1h = The wakeup flag is set when WU_SRC is low or goes low.
6ENR/W0hProgrammable wakeup flag enable.
0: Disable wakeup flag.
1: Enable wakeup flag.
5-0WU_SRCR/W0hWakeup source from the asynchronous AUX event bus.
Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU0 is 1.
If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read.
0h = AUX_EVCTL:EVSTAT0.AUXIO0
1h = AUX_EVCTL:EVSTAT0.AUXIO1
2h = AUX_EVCTL:EVSTAT0.AUXIO2
3h = AUX_EVCTL:EVSTAT0.AUXIO3
4h = AUX_EVCTL:EVSTAT0.AUXIO4
5h = AUX_EVCTL:EVSTAT0.AUXIO5
6h = AUX_EVCTL:EVSTAT0.AUXIO6
7h = AUX_EVCTL:EVSTAT0.AUXIO7
8h = AUX_EVCTL:EVSTAT0.AUXIO8
9h = AUX_EVCTL:EVSTAT0.AUXIO9
Ah = AUX_EVCTL:EVSTAT0.AUXIO10
Bh = AUX_EVCTL:EVSTAT0.AUXIO11
Ch = AUX_EVCTL:EVSTAT0.AUXIO12
Dh = AUX_EVCTL:EVSTAT0.AUXIO13
Eh = AUX_EVCTL:EVSTAT0.AUXIO14
Fh = AUX_EVCTL:EVSTAT0.AUXIO15
10h = AUX_EVCTL:EVSTAT1.AUXIO16
11h = AUX_EVCTL:EVSTAT1.AUXIO17
12h = AUX_EVCTL:EVSTAT1.AUXIO18
13h = AUX_EVCTL:EVSTAT1.AUXIO19
14h = AUX_EVCTL:EVSTAT1.AUXIO20
15h = AUX_EVCTL:EVSTAT1.AUXIO21
16h = AUX_EVCTL:EVSTAT1.AUXIO22
17h = AUX_EVCTL:EVSTAT1.AUXIO23
18h = AUX_EVCTL:EVSTAT1.AUXIO24
19h = AUX_EVCTL:EVSTAT1.AUXIO25
1Ah = AUX_EVCTL:EVSTAT1.AUXIO26
1Bh = AUX_EVCTL:EVSTAT1.AUXIO27
1Ch = AUX_EVCTL:EVSTAT1.AUXIO28
1Dh = AUX_EVCTL:EVSTAT1.AUXIO29
1Eh = AUX_EVCTL:EVSTAT1.AUXIO30
1Fh = AUX_EVCTL:EVSTAT1.AUXIO31
20h = AUX_EVCTL:EVSTAT2.MANUAL_EV
21h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2
22h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
23h = AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
24h = AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
25h = AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
26h = AUX_EVCTL:EVSTAT2.SCLK_LF
27h = AUX_EVCTL:EVSTAT2.PWR_DWN
28h = AUX_EVCTL:EVSTAT2.MCU_ACTIVE
29h = AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
2Ah = AUX_EVCTL:EVSTAT2.ACLK_REF
2Bh = AUX_EVCTL:EVSTAT2.MCU_EV
2Ch = AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
2Dh = AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
2Eh = AUX_EVCTL:EVSTAT2.AUX_COMPA
2Fh = AUX_EVCTL:EVSTAT2.AUX_COMPB
30h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
31h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
32h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
33h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
34h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
35h = AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
36h = AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
37h = AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
38h = AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
39h = AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
3Ah = AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
3Bh = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
3Ch = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
3Dh = AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
3Fh = No event.

20.8.9.4 PROGWU1CFG Register (Offset = Ch) [Reset = 00000000h]

PROGWU1CFG is shown in Figure 20-157 and described in Table 20-179.

Return to the Summary Table.

Programmable Wakeup 1 Configuration
Configure this register to enable a customized AUX wakeup flag. The wakeup flag will be captured by AON_PMCTL which responds according to the current operational mode. You can select WUFLAGS.PROG_WU1 to trigger execution of a programmable AUX_SCE vector by configuration of VECCFGn. You need to follow the procedure described in WUFLAGSCLR to clear this flag. You need to follow the procedure described in WUGATE to configure it.

Figure 20-157 PROGWU1CFG Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDPOLENWU_SRC
R-0hR/W-0hR/W-0hR/W-0h
Table 20-179 PROGWU1CFG Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7POLR/W0hPolarity of WU_SRC.
The procedure used to clear the wakeup flag decides level or edge sensitivity, see WUFLAGSCLR.PROG_WU1.
0h = The wakeup flag is set when WU_SRC is high or goes high.
1h = The wakeup flag is set when WU_SRC is low or goes low.
6ENR/W0hProgrammable wakeup flag enable.
0: Disable wakeup flag.
1: Enable wakeup flag.
5-0WU_SRCR/W0hWakeup source from the asynchronous AUX event bus.
Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU1 is 1.
If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read.
0h = AUX_EVCTL:EVSTAT0.AUXIO0
1h = AUX_EVCTL:EVSTAT0.AUXIO1
2h = AUX_EVCTL:EVSTAT0.AUXIO2
3h = AUX_EVCTL:EVSTAT0.AUXIO3
4h = AUX_EVCTL:EVSTAT0.AUXIO4
5h = AUX_EVCTL:EVSTAT0.AUXIO5
6h = AUX_EVCTL:EVSTAT0.AUXIO6
7h = AUX_EVCTL:EVSTAT0.AUXIO7
8h = AUX_EVCTL:EVSTAT0.AUXIO8
9h = AUX_EVCTL:EVSTAT0.AUXIO9
Ah = AUX_EVCTL:EVSTAT0.AUXIO10
Bh = AUX_EVCTL:EVSTAT0.AUXIO11
Ch = AUX_EVCTL:EVSTAT0.AUXIO12
Dh = AUX_EVCTL:EVSTAT0.AUXIO13
Eh = AUX_EVCTL:EVSTAT0.AUXIO14
Fh = AUX_EVCTL:EVSTAT0.AUXIO15
10h = AUX_EVCTL:EVSTAT1.AUXIO16
11h = AUX_EVCTL:EVSTAT1.AUXIO17
12h = AUX_EVCTL:EVSTAT1.AUXIO18
13h = AUX_EVCTL:EVSTAT1.AUXIO19
14h = AUX_EVCTL:EVSTAT1.AUXIO20
15h = AUX_EVCTL:EVSTAT1.AUXIO21
16h = AUX_EVCTL:EVSTAT1.AUXIO22
17h = AUX_EVCTL:EVSTAT1.AUXIO23
18h = AUX_EVCTL:EVSTAT1.AUXIO24
19h = AUX_EVCTL:EVSTAT1.AUXIO25
1Ah = AUX_EVCTL:EVSTAT1.AUXIO26
1Bh = AUX_EVCTL:EVSTAT1.AUXIO27
1Ch = AUX_EVCTL:EVSTAT1.AUXIO28
1Dh = AUX_EVCTL:EVSTAT1.AUXIO29
1Eh = AUX_EVCTL:EVSTAT1.AUXIO30
1Fh = AUX_EVCTL:EVSTAT1.AUXIO31
20h = AUX_EVCTL:EVSTAT2.MANUAL_EV
21h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2
22h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
23h = AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
24h = AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
25h = AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
26h = AUX_EVCTL:EVSTAT2.SCLK_LF
27h = AUX_EVCTL:EVSTAT2.PWR_DWN
28h = AUX_EVCTL:EVSTAT2.MCU_ACTIVE
29h = AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
2Ah = AUX_EVCTL:EVSTAT2.ACLK_REF
2Bh = AUX_EVCTL:EVSTAT2.MCU_EV
2Ch = AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
2Dh = AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
2Eh = AUX_EVCTL:EVSTAT2.AUX_COMPA
2Fh = AUX_EVCTL:EVSTAT2.AUX_COMPB
30h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
31h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
32h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
33h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
34h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
35h = AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
36h = AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
37h = AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
38h = AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
39h = AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
3Ah = AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
3Bh = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
3Ch = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
3Dh = AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
3Fh = No event.

20.8.9.5 PROGWU2CFG Register (Offset = 10h) [Reset = 00000000h]

PROGWU2CFG is shown in Figure 20-158 and described in Table 20-180.

Return to the Summary Table.

Programmable Wakeup 2 Configuration
Configure this register to enable a customized AUX wakeup flag. The wakeup flag will be captured by AON_PMCTL which responds according to the current operational mode. You can select WUFLAGS.PROG_WU2 to trigger execution of a programmable AUX_SCE vector by configuration of VECCFGn. You need to follow the procedure described in WUFLAGSCLR to clear this flag. You need to follow the procedure described in WUGATE to configure it.

Figure 20-158 PROGWU2CFG Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDPOLENWU_SRC
R-0hR/W-0hR/W-0hR/W-0h
Table 20-180 PROGWU2CFG Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7POLR/W0hPolarity of WU_SRC.
The procedure used to clear the wakeup flag decides level or edge sensitivity, see WUFLAGSCLR.PROG_WU2.
0h = The wakeup flag is set when WU_SRC is high or goes high.
1h = The wakeup flag is set when WU_SRC is low or goes low.
6ENR/W0hProgrammable wakeup flag enable.
0: Disable wakeup flag.
1: Enable wakeup flag.
5-0WU_SRCR/W0hWakeup source from the asynchronous AUX event bus.
Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU2 is 1.
If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read.
0h = AUX_EVCTL:EVSTAT0.AUXIO0
1h = AUX_EVCTL:EVSTAT0.AUXIO1
2h = AUX_EVCTL:EVSTAT0.AUXIO2
3h = AUX_EVCTL:EVSTAT0.AUXIO3
4h = AUX_EVCTL:EVSTAT0.AUXIO4
5h = AUX_EVCTL:EVSTAT0.AUXIO5
6h = AUX_EVCTL:EVSTAT0.AUXIO6
7h = AUX_EVCTL:EVSTAT0.AUXIO7
8h = AUX_EVCTL:EVSTAT0.AUXIO8
9h = AUX_EVCTL:EVSTAT0.AUXIO9
Ah = AUX_EVCTL:EVSTAT0.AUXIO10
Bh = AUX_EVCTL:EVSTAT0.AUXIO11
Ch = AUX_EVCTL:EVSTAT0.AUXIO12
Dh = AUX_EVCTL:EVSTAT0.AUXIO13
Eh = AUX_EVCTL:EVSTAT0.AUXIO14
Fh = AUX_EVCTL:EVSTAT0.AUXIO15
10h = AUX_EVCTL:EVSTAT1.AUXIO16
11h = AUX_EVCTL:EVSTAT1.AUXIO17
12h = AUX_EVCTL:EVSTAT1.AUXIO18
13h = AUX_EVCTL:EVSTAT1.AUXIO19
14h = AUX_EVCTL:EVSTAT1.AUXIO20
15h = AUX_EVCTL:EVSTAT1.AUXIO21
16h = AUX_EVCTL:EVSTAT1.AUXIO22
17h = AUX_EVCTL:EVSTAT1.AUXIO23
18h = AUX_EVCTL:EVSTAT1.AUXIO24
19h = AUX_EVCTL:EVSTAT1.AUXIO25
1Ah = AUX_EVCTL:EVSTAT1.AUXIO26
1Bh = AUX_EVCTL:EVSTAT1.AUXIO27
1Ch = AUX_EVCTL:EVSTAT1.AUXIO28
1Dh = AUX_EVCTL:EVSTAT1.AUXIO29
1Eh = AUX_EVCTL:EVSTAT1.AUXIO30
1Fh = AUX_EVCTL:EVSTAT1.AUXIO31
20h = AUX_EVCTL:EVSTAT2.MANUAL_EV
21h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2
22h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
23h = AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
24h = AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
25h = AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
26h = AUX_EVCTL:EVSTAT2.SCLK_LF
27h = AUX_EVCTL:EVSTAT2.PWR_DWN
28h = AUX_EVCTL:EVSTAT2.MCU_ACTIVE
29h = AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
2Ah = AUX_EVCTL:EVSTAT2.ACLK_REF
2Bh = AUX_EVCTL:EVSTAT2.MCU_EV
2Ch = AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
2Dh = AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
2Eh = AUX_EVCTL:EVSTAT2.AUX_COMPA
2Fh = AUX_EVCTL:EVSTAT2.AUX_COMPB
30h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
31h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
32h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
33h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
34h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
35h = AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
36h = AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
37h = AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
38h = AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
39h = AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
3Ah = AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
3Bh = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
3Ch = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
3Dh = AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
3Fh = No event.

20.8.9.6 PROGWU3CFG Register (Offset = 14h) [Reset = 00000000h]

PROGWU3CFG is shown in Figure 20-159 and described in Table 20-181.

Return to the Summary Table.

Programmable Wakeup 3 Configuration
Configure this register to enable a customized AUX wakeup flag. The wakeup flag will be captured by AON_PMCTL which responds according to the current operational mode. You can select WUFLAGS.PROG_WU3 to trigger execution of a programmable AUX_SCE vector by configuration of VECCFGn. You need to follow the procedure described in WUFLAGSCLR to clear this flag. You need to follow the procedure described in WUGATE to configure it.

Figure 20-159 PROGWU3CFG Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDPOLENWU_SRC
R-0hR/W-0hR/W-0hR/W-0h
Table 20-181 PROGWU3CFG Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7POLR/W0hPolarity of WU_SRC.
The procedure used to clear the wakeup flag decides level or edge sensitivity, see WUFLAGSCLR.PROG_WU3.
0h = The wakeup flag is set when WU_SRC is high or goes high.
1h = The wakeup flag is set when WU_SRC is low or goes low.
6ENR/W0hProgrammable wakeup flag enable.
0: Disable wakeup flag.
1: Enable wakeup flag.
5-0WU_SRCR/W0hWakeup source from the asynchronous AUX event bus.
Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU3 is 1.
If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read.
0h = AUX_EVCTL:EVSTAT0.AUXIO0
1h = AUX_EVCTL:EVSTAT0.AUXIO1
2h = AUX_EVCTL:EVSTAT0.AUXIO2
3h = AUX_EVCTL:EVSTAT0.AUXIO3
4h = AUX_EVCTL:EVSTAT0.AUXIO4
5h = AUX_EVCTL:EVSTAT0.AUXIO5
6h = AUX_EVCTL:EVSTAT0.AUXIO6
7h = AUX_EVCTL:EVSTAT0.AUXIO7
8h = AUX_EVCTL:EVSTAT0.AUXIO8
9h = AUX_EVCTL:EVSTAT0.AUXIO9
Ah = AUX_EVCTL:EVSTAT0.AUXIO10
Bh = AUX_EVCTL:EVSTAT0.AUXIO11
Ch = AUX_EVCTL:EVSTAT0.AUXIO12
Dh = AUX_EVCTL:EVSTAT0.AUXIO13
Eh = AUX_EVCTL:EVSTAT0.AUXIO14
Fh = AUX_EVCTL:EVSTAT0.AUXIO15
10h = AUX_EVCTL:EVSTAT1.AUXIO16
11h = AUX_EVCTL:EVSTAT1.AUXIO17
12h = AUX_EVCTL:EVSTAT1.AUXIO18
13h = AUX_EVCTL:EVSTAT1.AUXIO19
14h = AUX_EVCTL:EVSTAT1.AUXIO20
15h = AUX_EVCTL:EVSTAT1.AUXIO21
16h = AUX_EVCTL:EVSTAT1.AUXIO22
17h = AUX_EVCTL:EVSTAT1.AUXIO23
18h = AUX_EVCTL:EVSTAT1.AUXIO24
19h = AUX_EVCTL:EVSTAT1.AUXIO25
1Ah = AUX_EVCTL:EVSTAT1.AUXIO26
1Bh = AUX_EVCTL:EVSTAT1.AUXIO27
1Ch = AUX_EVCTL:EVSTAT1.AUXIO28
1Dh = AUX_EVCTL:EVSTAT1.AUXIO29
1Eh = AUX_EVCTL:EVSTAT1.AUXIO30
1Fh = AUX_EVCTL:EVSTAT1.AUXIO31
20h = AUX_EVCTL:EVSTAT2.MANUAL_EV
21h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2
22h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
23h = AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
24h = AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
25h = AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
26h = AUX_EVCTL:EVSTAT2.SCLK_LF
27h = AUX_EVCTL:EVSTAT2.PWR_DWN
28h = AUX_EVCTL:EVSTAT2.MCU_ACTIVE
29h = AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
2Ah = AUX_EVCTL:EVSTAT2.ACLK_REF
2Bh = AUX_EVCTL:EVSTAT2.MCU_EV
2Ch = AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
2Dh = AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
2Eh = AUX_EVCTL:EVSTAT2.AUX_COMPA
2Fh = AUX_EVCTL:EVSTAT2.AUX_COMPB
30h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
31h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
32h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
33h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
34h = AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
35h = AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
36h = AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
37h = AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
38h = AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
39h = AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
3Ah = AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
3Bh = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
3Ch = AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
3Dh = AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
3Fh = No event.

20.8.9.7 SWWUTRIG Register (Offset = 18h) [Reset = 00000000h]

SWWUTRIG is shown in Figure 20-160 and described in Table 20-182.

Return to the Summary Table.

Software Wakeup Triggers
System CPU uses these wakeup flags to perform handshaking with AUX_SCE. The wakeup flags can change the operational mode of AUX and guarantees a non-zero SCE clock rate. AUX_SCE wakeup vectors are configured in VECCFGn.

Figure 20-160 SWWUTRIG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSW_WU3SW_WU2SW_WU1SW_WU0
R-0hW-0hW-0hW-0hW-0h
Table 20-182 SWWUTRIG Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3SW_WU3W0hSoftware wakeup 3 trigger.
0: No effect.
1: Set WUFLAGS.SW_WU3 and trigger AUX wakeup.
2SW_WU2W0hSoftware wakeup 2 trigger.
0: No effect.
1: Set WUFLAGS.SW_WU2 and trigger AUX wakeup.
1SW_WU1W0hSoftware wakeup 1 trigger.
0: No effect.
1: Set WUFLAGS.SW_WU1 and trigger AUX wakeup.
0SW_WU0W0hSoftware wakeup 0 trigger.
0: No effect.
1: Set WUFLAGS.SW_WU0 and trigger AUX wakeup.

20.8.9.8 WUFLAGS Register (Offset = 1Ch) [Reset = 00000000h]

WUFLAGS is shown in Figure 20-161 and described in Table 20-183.

Return to the Summary Table.

Wakeup Flags
This register holds the eight AUX wakeup flags. Each flag can cause AUX operational mode to change as given in OPMODEREQ. To clear flag n you must set bit n in WUFLAGSCLR until flag n is read as 0. You must clear bit n in WUFLAGSCLR before flag n can be set again.

Figure 20-161 WUFLAGS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
SW_WU3SW_WU2SW_WU1SW_WU0PROG_WU3PROG_WU2PROG_WU1PROG_WU0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 20-183 WUFLAGS Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7SW_WU3R0hSoftware wakeup 3 flag.
0: Software wakeup 3 not triggered.
1: Software wakeup 3 triggered.
6SW_WU2R0hSoftware wakeup 2 flag.
0: Software wakeup 2 not triggered.
1: Software wakeup 2 triggered.
5SW_WU1R0hSoftware wakeup 1 flag.
0: Software wakeup 1 not triggered.
1: Software wakeup 1 triggered.
4SW_WU0R0hSoftware wakeup 0 flag.
0: Software wakeup 0 not triggered.
1: Software wakeup 0 triggered.
3PROG_WU3R0hProgrammable wakeup 3.
0: Programmable wakeup 3 not triggered.
1: Programmable wakeup 3 triggered.
2PROG_WU2R0hProgrammable wakeup 2.
0: Programmable wakeup 2 not triggered.
1: Programmable wakeup 2 triggered.
1PROG_WU1R0hProgrammable wakeup 1.
0: Programmable wakeup 1 not triggered.
1: Programmable wakeup 1 triggered.
0PROG_WU0R0hProgrammable wakeup 0.
0: Programmable wakeup 0 not triggered.
1: Programmable wakeup 0 triggered.

20.8.9.9 WUFLAGSCLR Register (Offset = 20h) [Reset = 0000000Fh]

WUFLAGSCLR is shown in Figure 20-162 and described in Table 20-184.

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Wakeup Flags Clear
This register clears AUX wakeup flags WUFLAGS.
To clear programmable wakeup flags you must disable the AUX wakeup output first. After the programmable wakeup flags are cleared you must re-enable the AUX wakeup output. Write WUGATE to disable or enable the AUX wakeup output. This procedure is not required when you want to clear a software-triggered wakeup.

Figure 20-162 WUFLAGSCLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
SW_WU3SW_WU2SW_WU1SW_WU0PROG_WU3PROG_WU2PROG_WU1PROG_WU0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-1hR/W-1hR/W-1hR/W-1h
Table 20-184 WUFLAGSCLR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7SW_WU3R/W0hClear software wakeup flag 3.
0: No effect.
1: Clear WUFLAGS.SW_WU3. Keep high until WUFLAGS.SW_WU3 is 0.
6SW_WU2R/W0hClear software wakeup flag 2.
0: No effect.
1: Clear WUFLAGS.SW_WU2. Keep high until WUFLAGS.SW_WU2 is 0.
5SW_WU1R/W0hClear software wakeup flag 1.
0: No effect.
1: Clear WUFLAGS.SW_WU1. Keep high until WUFLAGS.SW_WU1 is 0.
4SW_WU0R/W0hClear software wakeup flag 0.
0: No effect.
1: Clear WUFLAGS.SW_WU0. Keep high until WUFLAGS.SW_WU0 is 0.
3PROG_WU3R/W1hProgrammable wakeup flag 3.
0: No effect.
1: Clear WUFLAGS.PROG_WU3. Keep high until WUFLAGS.PROG_WU3 is 0.
The wakeup flag becomes edge sensitive if you write PROG_WU3 to 0 when PROGWU3CFG.EN is 1.
The wakeup flag becomes level sensitive if you write PROG_WU3 to 0 when PROGWU3CFG.EN is 0, then set PROGWU3CFG.EN.
2PROG_WU2R/W1hProgrammable wakeup flag 2.
0: No effect.
1: Clear WUFLAGS.PROG_WU2. Keep high until WUFLAGS.PROG_WU2 is 0.
The wakeup flag becomes edge sensitive if you write PROG_WU2 to 0 when PROGWU2CFG.EN is 1.
The wakeup flag becomes level sensitive if you write PROG_WU2 to 0 when PROGWU2CFG.EN is 0, then set PROGWU2CFG.EN.
1PROG_WU1R/W1hProgrammable wakeup flag 1.
0: No effect.
1: Clear WUFLAGS.PROG_WU1. Keep high until WUFLAGS.PROG_WU1 is 0.
The wakeup flag becomes edge sensitive if you write PROG_WU1 to 0 when PROGWU1CFG.EN is 1.
The wakeup flag becomes level sensitive if you write PROG_WU1 to 0 when PROGWU1CFG.EN is 0, then set PROGWU1CFG.EN.
0PROG_WU0R/W1hProgrammable wakeup flag 0.
0: No effect.
1: Clear WUFLAGS.PROG_WU0. Keep high until WUFLAGS.PROG_WU0 is 0.
The wakeup flag becomes edge sensitive if you write PROG_WU0 to 0 when PROGWU0CFG.EN is 1.
The wakeup flag becomes level sensitive if you write PROG_WU0 to 0 when PROGWU0CFG.EN is 0, then set PROGWU0CFG.EN.

20.8.9.10 WUGATE Register (Offset = 24h) [Reset = 00000000h]

WUGATE is shown in Figure 20-163 and described in Table 20-185.

Return to the Summary Table.

Wakeup Gate
You must disable the AUX wakeup output:
- Before you clear a programmable wakeup flag.
- Before you change the value of [PROGWUnCFG.EN] or [PROGWUnCFG.WU_SRC].
The AUX wakeup output must be re-enabled after clear operation or programmable wakeup configuration.

Figure 20-163 WUGATE Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDEN
R-0hR/W-0h
Table 20-185 WUGATE Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ENR/W0hWakeup output enable.
0: Disable AUX wakeup output.
1: Enable AUX wakeup output.

20.8.9.11 VECCFG0 Register (Offset = 28h) [Reset = 00000000h]

VECCFG0 is shown in Figure 20-164 and described in Table 20-186.

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Vector Configuration 0
AUX_SCE wakeup vector 0 configuration

Figure 20-164 VECCFG0 Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDVEC_EV
R-0hR/W-0h
Table 20-186 VECCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0VEC_EVR/W0hSelect trigger event for vector 0.
Non-enumerated values are treated as NONE.
0h = Vector is disabled.
1h = WUFLAGS.PROG_WU0
2h = WUFLAGS.PROG_WU1
3h = WUFLAGS.PROG_WU2
4h = WUFLAGS.PROG_WU3
5h = WUFLAGS.SW_WU0
6h = WUFLAGS.SW_WU1
7h = WUFLAGS.SW_WU2
8h = WUFLAGS.SW_WU3
9h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY

20.8.9.12 VECCFG1 Register (Offset = 2Ch) [Reset = 00000000h]

VECCFG1 is shown in Figure 20-165 and described in Table 20-187.

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Vector Configuration 1
AUX_SCE wakeup vector 1 configuration

Figure 20-165 VECCFG1 Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDVEC_EV
R-0hR/W-0h
Table 20-187 VECCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0VEC_EVR/W0hSelect trigger event for vector 1.
Non-enumerated values are treated as NONE.
0h = Vector is disabled.
1h = WUFLAGS.PROG_WU0
2h = WUFLAGS.PROG_WU1
3h = WUFLAGS.PROG_WU2
4h = WUFLAGS.PROG_WU3
5h = WUFLAGS.SW_WU0
6h = WUFLAGS.SW_WU1
7h = WUFLAGS.SW_WU2
8h = WUFLAGS.SW_WU3
9h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY

20.8.9.13 VECCFG2 Register (Offset = 30h) [Reset = 00000000h]

VECCFG2 is shown in Figure 20-166 and described in Table 20-188.

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Vector Configuration 2
AUX_SCE wakeup vector 2 configuration

Figure 20-166 VECCFG2 Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDVEC_EV
R-0hR/W-0h
Table 20-188 VECCFG2 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0VEC_EVR/W0hSelect trigger event for vector 2.
Non-enumerated values are treated as NONE.
0h = Vector is disabled.
1h = WUFLAGS.PROG_WU0
2h = WUFLAGS.PROG_WU1
3h = WUFLAGS.PROG_WU2
4h = WUFLAGS.PROG_WU3
5h = WUFLAGS.SW_WU0
6h = WUFLAGS.SW_WU1
7h = WUFLAGS.SW_WU2
8h = WUFLAGS.SW_WU3
9h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY

20.8.9.14 VECCFG3 Register (Offset = 34h) [Reset = 00000000h]

VECCFG3 is shown in Figure 20-167 and described in Table 20-189.

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Vector Configuration 3
AUX_SCE wakeup vector 3 configuration

Figure 20-167 VECCFG3 Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDVEC_EV
R-0hR/W-0h
Table 20-189 VECCFG3 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0VEC_EVR/W0hSelect trigger event for vector 3.
Non-enumerated values are treated as NONE.
0h = Vector is disabled.
1h = WUFLAGS.PROG_WU0
2h = WUFLAGS.PROG_WU1
3h = WUFLAGS.PROG_WU2
4h = WUFLAGS.PROG_WU3
5h = WUFLAGS.SW_WU0
6h = WUFLAGS.SW_WU1
7h = WUFLAGS.SW_WU2
8h = WUFLAGS.SW_WU3
9h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY

20.8.9.15 VECCFG4 Register (Offset = 38h) [Reset = 00000000h]

VECCFG4 is shown in Figure 20-168 and described in Table 20-190.

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Vector Configuration 4
AUX_SCE wakeup vector 4 configuration

Figure 20-168 VECCFG4 Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDVEC_EV
R-0hR/W-0h
Table 20-190 VECCFG4 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0VEC_EVR/W0hSelect trigger event for vector 4.
Non-enumerated values are treated as NONE.
0h = Vector is disabled.
1h = WUFLAGS.PROG_WU0
2h = WUFLAGS.PROG_WU1
3h = WUFLAGS.PROG_WU2
4h = WUFLAGS.PROG_WU3
5h = WUFLAGS.SW_WU0
6h = WUFLAGS.SW_WU1
7h = WUFLAGS.SW_WU2
8h = WUFLAGS.SW_WU3
9h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY

20.8.9.16 VECCFG5 Register (Offset = 3Ch) [Reset = 00000000h]

VECCFG5 is shown in Figure 20-169 and described in Table 20-191.

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Vector Configuration 5
AUX_SCE wakeup vector 5 configuration

Figure 20-169 VECCFG5 Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDVEC_EV
R-0hR/W-0h
Table 20-191 VECCFG5 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0VEC_EVR/W0hSelect trigger event for vector 5.
Non-enumerated values are treated as NONE.
0h = Vector is disabled.
1h = WUFLAGS.PROG_WU0
2h = WUFLAGS.PROG_WU1
3h = WUFLAGS.PROG_WU2
4h = WUFLAGS.PROG_WU3
5h = WUFLAGS.SW_WU0
6h = WUFLAGS.SW_WU1
7h = WUFLAGS.SW_WU2
8h = WUFLAGS.SW_WU3
9h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY

20.8.9.17 VECCFG6 Register (Offset = 40h) [Reset = 00000000h]

VECCFG6 is shown in Figure 20-170 and described in Table 20-192.

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Vector Configuration 6
AUX_SCE wakeup vector 6 configuration

Figure 20-170 VECCFG6 Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDVEC_EV
R-0hR/W-0h
Table 20-192 VECCFG6 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0VEC_EVR/W0hSelect trigger event for vector 6.
Non-enumerated values are treated as NONE.
0h = Vector is disabled.
1h = WUFLAGS.PROG_WU0
2h = WUFLAGS.PROG_WU1
3h = WUFLAGS.PROG_WU2
4h = WUFLAGS.PROG_WU3
5h = WUFLAGS.SW_WU0
6h = WUFLAGS.SW_WU1
7h = WUFLAGS.SW_WU2
8h = WUFLAGS.SW_WU3
9h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY

20.8.9.18 VECCFG7 Register (Offset = 44h) [Reset = 00000000h]

VECCFG7 is shown in Figure 20-171 and described in Table 20-193.

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Vector Configuration 7
AUX_SCE wakeup vector 7 configuration

Figure 20-171 VECCFG7 Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDVEC_EV
R-0hR/W-0h
Table 20-193 VECCFG7 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0VEC_EVR/W0hSelect trigger event for vector 7.
Non-enumerated values are treated as NONE.
0h = Vector is disabled.
1h = WUFLAGS.PROG_WU0
2h = WUFLAGS.PROG_WU1
3h = WUFLAGS.PROG_WU2
4h = WUFLAGS.PROG_WU3
5h = WUFLAGS.SW_WU0
6h = WUFLAGS.SW_WU1
7h = WUFLAGS.SW_WU2
8h = WUFLAGS.SW_WU3
9h = AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY

20.8.9.19 EVSYNCRATE Register (Offset = 48h) [Reset = 00000000h]

EVSYNCRATE is shown in Figure 20-172 and described in Table 20-194.

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Event Synchronization Rate
Configure synchronization rate for certain events to the synchronous AUX event bus.
You must select SCE rate when AUX_SCE uses the event. You must select AUX bus rate when system CPU uses the event.
SCE rate equals rate configured in AON_PMCTL:AUXSCECLK. AUX bus rate equals SCE rate, or SCLK_HF divided by two when MCU domain is active.

Figure 20-172 EVSYNCRATE Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDAUX_COMPA_SYNC_RATEAUX_COMPB_SYNC_RATEAUX_TIMER2_SYNC_RATE
R-0hR/W-0hR/W-0hR/W-0h
Table 20-194 EVSYNCRATE Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2AUX_COMPA_SYNC_RATER/W0hSelect synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPA event.
0h = SCE rate
1h = AUX bus rate
1AUX_COMPB_SYNC_RATER/W0hSelect synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPB event.
0h = SCE rate
1h = AUX bus rate
0AUX_TIMER2_SYNC_RATER/W0hSelect synchronization rate for:
- AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
- AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
- AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
- AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
- AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
0h = SCE rate
1h = AUX bus rate

20.8.9.20 PEROPRATE Register (Offset = 4Ch) [Reset = 00000000h]

PEROPRATE is shown in Figure 20-173 and described in Table 20-195.

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Peripheral Operational Rate
Some AUX peripherals are operated at either SCE or at AUX bus rate.
You must select SCE rate when AUX_SCE uses such peripheral or an event produced by it. You must select AUX bus rate when system CPU uses such peripheral.
SCE rate equals rate configured in AON_PMCTL:AUXSCECLK. AUX bus rate equals SCE rate, or SCLK_HF divided by 2 when MCU domain is active.

Figure 20-173 PEROPRATE Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDANAIF_DAC_OP_RATETIMER01_OP_RATESPIM_OP_RATEMAC_OP_RATE
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 20-195 PEROPRATE Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3ANAIF_DAC_OP_RATER/W0hSelect operational rate for AUX_ANAIF DAC sample clock state machine.
0h = SCE rate
1h = AUX bus rate
2TIMER01_OP_RATER/W0hSelect operational rate for AUX_TIMER01.
0h = SCE rate
1h = AUX bus rate
1SPIM_OP_RATER/W0hSelect operational rate for AUX_SPIM.
0h = SCE rate
1h = AUX bus rate
0MAC_OP_RATER/W0hSelect operational rate for AUX_MAC.
0h = SCE rate
1h = AUX bus rate

20.8.9.21 ADCCLKCTL Register (Offset = 50h) [Reset = 00000000h]

ADCCLKCTL is shown in Figure 20-174 and described in Table 20-196.

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ADC Clock Control

Figure 20-174 ADCCLKCTL Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDACKREQ
R-0hR-0hR/W-0h
Table 20-196 ADCCLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1ACKR0hClock acknowledgement.
0: ADC clock is disabled.
1: ADC clock is enabled.
0REQR/W0hADC clock request.
0: Disable ADC clock.
1: Enable ADC clock.
Only modify REQ when equal to ACK.

20.8.9.22 TDCCLKCTL Register (Offset = 54h) [Reset = 00000000h]

TDCCLKCTL is shown in Figure 20-175 and described in Table 20-197.

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TDC Counter Clock Control
Controls if the AUX_TDC counter clock source is enabled. TDC counter clock source is configured in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL.

Figure 20-175 TDCCLKCTL Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDACKREQ
R-0hR-0hR/W-0h
Table 20-197 TDCCLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1ACKR0hTDC counter clock acknowledgement.
0: TDC counter clock is disabled.
1: TDC counter clock is enabled.
0REQR/W0hTDC counter clock request.
0: Disable TDC counter clock.
1: Enable TDC counter clock.
Only modify REQ when equal to ACK.

20.8.9.23 TDCREFCLKCTL Register (Offset = 58h) [Reset = 00000000h]

TDCREFCLKCTL is shown in Figure 20-176 and described in Table 20-198.

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TDC Reference Clock Control
Controls if the AUX_TDC reference clock source is enabled. This clock is compared against the AUX_TDC counter clock. TDC reference clock source is configured in DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL.

Figure 20-176 TDCREFCLKCTL Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDACKREQ
R-0hR-0hR/W-0h
Table 20-198 TDCREFCLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1ACKR0hTDC reference clock acknowledgement.
0: TDC reference clock is disabled.
1: TDC reference clock is enabled.
0REQR/W0hTDC reference clock request.
0: Disable TDC reference clock.
1: Enable TDC reference clock.
Only modify REQ when equal to ACK.

20.8.9.24 TIMER2CLKCTL Register (Offset = 5Ch) [Reset = 00000000h]

TIMER2CLKCTL is shown in Figure 20-177 and described in Table 20-199.

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AUX_TIMER2 Clock Control
Access to AUX_TIMER2 is only possible when TIMER2CLKSTAT.STAT is different from NONE.

Figure 20-177 TIMER2CLKCTL Register
313029282726252423222120191817161514131211109876543210
RESERVEDSRC
R-0hR/W-0h
Table 20-199 TIMER2CLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0SRCR/W0hSelect clock source for AUX_TIMER2.
Update is only accepted if SRC equals TIMER2CLKSTAT.STAT or TIMER2CLKSWITCH.RDY is 1.
It is recommended to select NONE only when TIMER2BRIDGE.BUSY is 0.
A non-enumerated value is ignored.
0h = no clock
1h = SCLK_LF
2h = SCLK_MF
4h = SCLK_HF / 2

20.8.9.25 TIMER2CLKSTAT Register (Offset = 60h) [Reset = 00000000h]

TIMER2CLKSTAT is shown in Figure 20-178 and described in Table 20-200.

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AUX_TIMER2 Clock Status

Figure 20-178 TIMER2CLKSTAT Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 20-200 TIMER2CLKSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0STATR0hAUX_TIMER2 clock source status.
0h = No clock
1h = SCLK_LF
2h = SCLK_MF
4h = SCLK_HF / 2

20.8.9.26 TIMER2CLKSWITCH Register (Offset = 64h) [Reset = 00000001h]

TIMER2CLKSWITCH is shown in Figure 20-179 and described in Table 20-201.

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AUX_TIMER2 Clock Switch

Figure 20-179 TIMER2CLKSWITCH Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDRDY
R-0hR-1h
Table 20-201 TIMER2CLKSWITCH Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0RDYR1hStatus of clock switcher.
0: TIMER2CLKCTL.SRC is different from TIMER2CLKSTAT.STAT.
1: TIMER2CLKCTL.SRC equals TIMER2CLKSTAT.STAT.
RDY connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY.

20.8.9.27 TIMER2DBGCTL Register (Offset = 68h) [Reset = 00000000h]

TIMER2DBGCTL is shown in Figure 20-180 and described in Table 20-202.

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AUX_TIMER2 Debug Control

Figure 20-180 TIMER2DBGCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDBG_FREEZE_EN
R-0hR/W-0h
Table 20-202 TIMER2DBGCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0DBG_FREEZE_ENR/W0hDebug freeze enable.
0: AUX_TIMER2 does not halt when the system CPU halts in debug mode.
1: Halt AUX_TIMER2 when the system CPU halts in debug mode.

20.8.9.28 CLKSHIFTDET Register (Offset = 70h) [Reset = 00000001h]

CLKSHIFTDET is shown in Figure 20-181 and described in Table 20-203.

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Clock Shift Detection
A transition in the MCU domain state causes a non-accumulative change to the SCE clock period when the AUX clock rate is derived from SCLK_MF or SCLK_LF:
- A single SCE clock cycle is 6 thru 8 SCLK_HF cycles longer when MCU domain enters active state.
- A single SCE clock cycle is 6 thru 8 SCLK_HF cycles shorter when MCU domain exits active state.

AUX_SCE detects if such events occurred to the SCE clock during the time period between a clear of STAT and a read of STAT.

Figure 20-181 CLKSHIFTDET Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSTAT
R-0hR/W-1h
Table 20-203 CLKSHIFTDET Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0STATR/W1hClock shift detection.
Write:
0: Restart clock shift detection.
1: Do not use.
Read:
0: MCU domain did not enter or exit active state since you wrote 0 to STAT.
1: MCU domain entered or exited active state since you wrote 0 to STAT.

20.8.9.29 RECHARGETRIG Register (Offset = 74h) [Reset = 00000000h]

RECHARGETRIG is shown in Figure 20-182 and described in Table 20-204.

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VDDR Recharge Trigger

Figure 20-182 RECHARGETRIG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTRIG
R-0hR/W-0h
Table 20-204 RECHARGETRIG Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0TRIGR/W0hRecharge trigger.
0: No effect.
1: Request VDDR recharge.
Request VDDR recharge only when AUX_EVCTL:EVSTAT2.PWR_DWN is 1.
Follow this sequence when OPMODEREQ.REQ is LP:
- Set TRIG.
- Wait until AUX_EVCTL:EVSTAT2.VDDR_RECHARGE is 1.
- Clear TRIG.
- Wait until AUX_EVCTL:EVSTAT2.VDDR_RECHARGE is 0.
Follow this sequence when OPMODEREQ.REQ is PDA or PDLP:
- Set TRIG.
- Clear TRIG.

20.8.9.30 RECHARGEDET Register (Offset = 78h) [Reset = 00000000h]

RECHARGEDET is shown in Figure 20-183 and described in Table 20-205.

Return to the Summary Table.

VDDR Recharge Detection
Some applications can be sensitive to power noise caused by recharge of VDDR. You can detect if VDDR recharge occurs.

Figure 20-183 RECHARGEDET Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSTATEN
R-0hR-0hR/W-0h
Table 20-205 RECHARGEDET Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1STATR0hVDDR recharge detector status.
0: No recharge of VDDR has occurred since EN was set.
1: Recharge of VDDR has occurred since EN was set.
0ENR/W0hVDDR recharge detector enable.
0: Disable recharge detection. STAT becomes zero.
1: Enable recharge detection.

20.8.9.31 RTCSUBSECINC0 Register (Offset = 7Ch) [Reset = 00000000h]

RTCSUBSECINC0 is shown in Figure 20-184 and described in Table 20-206.

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Real Time Counter Sub Second Increment 0
INC15_0 will replace bits 15:0 in AON_RTC:SUBSECINC when RTCSUBSECINCCTL.UPD_REQ is set.

Figure 20-184 RTCSUBSECINC0 Register
313029282726252423222120191817161514131211109876543210
RESERVEDINC15_0
R-0hR/W-0h
Table 20-206 RTCSUBSECINC0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0INC15_0R/W0hNew value for bits 15:0 in AON_RTC:SUBSECINC.

20.8.9.32 RTCSUBSECINC1 Register (Offset = 80h) [Reset = 00000000h]

RTCSUBSECINC1 is shown in Figure 20-185 and described in Table 20-207.

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Real Time Counter Sub Second Increment 1
INC23_16 will replace bits 23:16 in AON_RTC:SUBSECINC when RTCSUBSECINCCTL.UPD_REQ is set.

Figure 20-185 RTCSUBSECINC1 Register
313029282726252423222120191817161514131211109876543210
RESERVEDINC23_16
R-0hR/W-0h
Table 20-207 RTCSUBSECINC1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0INC23_16R/W0hNew value for bits 23:16 in AON_RTC:SUBSECINC.

20.8.9.33 RTCSUBSECINCCTL Register (Offset = 84h) [Reset = 00000000h]

RTCSUBSECINCCTL is shown in Figure 20-186 and described in Table 20-208.

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Real Time Counter Sub Second Increment Control

Figure 20-186 RTCSUBSECINCCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDUPD_ACKUPD_REQ
R-0hR-0hR/W-0h
Table 20-208 RTCSUBSECINCCTL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1UPD_ACKR0hUpdate acknowledgement.
0: AON_RTC has not acknowledged UPD_REQ.
1: AON_RTC has acknowledged UPD_REQ.
0UPD_REQR/W0hRequest AON_RTC to update AON_RTC:SUBSECINC.
0: Clear request to update.
1: Set request to update.
Only change UPD_REQ when it equals UPD_ACK. Clear UPD_REQ after UPD_ACK is 1.

20.8.9.34 RTCSEC Register (Offset = 88h) [Reset = 00000000h]

RTCSEC is shown in Figure 20-187 and described in Table 20-209.

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Real Time Counter Second
System CPU must not access this register. Instead, system CPU must access AON_RTC:SEC.VALUE directly.

Figure 20-187 RTCSEC Register
313029282726252423222120191817161514131211109876543210
RESERVEDSEC
R-0hR-0h
Table 20-209 RTCSEC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0SECR0hBits 15:0 in AON_RTC:SEC.VALUE.
Follow this procedure to get the correct value:
- Do two dummy reads of SEC.
- Then read SEC until two consecutive reads are equal.

20.8.9.35 RTCSUBSEC Register (Offset = 8Ch) [Reset = 00000000h]

RTCSUBSEC is shown in Figure 20-188 and described in Table 20-210.

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Real Time Counter Sub-Second
System CPU must not access this register. Instead, system CPU must access AON_RTC:SUBSEC.VALUE directly.

Figure 20-188 RTCSUBSEC Register
313029282726252423222120191817161514131211109876543210
RESERVEDSUBSEC
R-0hR-0h
Table 20-210 RTCSUBSEC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0SUBSECR0hBits 31:16 in AON_RTC:SUBSEC.VALUE.
Follow this procedure to get the correct value:
- Do two dummy reads SUBSEC.
- Then read SUBSEC until two consecutive reads are equal.

20.8.9.36 RTCEVCLR Register (Offset = 90h) [Reset = 00000000h]

RTCEVCLR is shown in Figure 20-189 and described in Table 20-211.

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AON_RTC Event Clear
Request to clear events:
- AON_RTC:EVFLAGS.CH2.
- AON_RTC:EVFLAGS.CH2 delayed version.
- AUX_EVCTL:EVSTAT2.AON_RTC_CH2.
- AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY.

Figure 20-189 RTCEVCLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRTC_CH2_EV_CLR
R-0hR/W-0h
Table 20-211 RTCEVCLR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0RTC_CH2_EV_CLRR/W0hClear events from AON_RTC channel 2.
0: No effect.
1: Clear events from AON_RTC channel 2.
Keep RTC_CH2_EV_CLR high until AUX_EVCTL:EVSTAT2.AON_RTC_CH2 and AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY are 0.

20.8.9.37 BATMONBAT Register (Offset = 94h) [Reset = 00000000h]

BATMONBAT is shown in Figure 20-190 and described in Table 20-212.

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AON_BATMON Battery Voltage Value
Read access to AON_BATMON:BAT. System CPU must not access this register. Instead, system CPU must access AON_BATMON:BAT directly. AON_BATMON:BAT updates during VDDR recharge or active operational mode.

Figure 20-190 BATMONBAT Register
313029282726252423222120191817161514131211109876543210
RESERVEDINTFRAC
R-0hRH-0hR-0h
Table 20-212 BATMONBAT Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10-8INTRH0hSee AON_BATMON:BAT.INT.
Follow this procedure to get the correct value:
- Do two dummy reads of INT.
- Then read INT until two consecutive reads are equal.
7-0FRACR0hSee AON_BATMON:BAT.FRAC.
Follow this procedure to get the correct value:
- Do two dummy reads of FRAC.
- Then read FRAC until two consecutive reads are equal.

20.8.9.38 BATMONTEMP Register (Offset = 9Ch) [Reset = 00000000h]

BATMONTEMP is shown in Figure 20-191 and described in Table 20-213.

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AON_BATMON Temperature Value
Read access to AON_BATMON:TEMP. System CPU must not access this register. Instead, system CPU must access AON_BATMON:TEMP directly. AON_BATMON:TEMP updates during VDDR recharge or active operational mode.

Figure 20-191 BATMONTEMP Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
SIGNINTFRAC
R-0hRH-0hR-0h
Table 20-213 BATMONTEMP Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-11SIGNR0hSign extension of INT.
Follow this procedure to get the correct value:
- Do two dummy reads of SIGN.
- Then read SIGN until two consecutive reads are equal.
10-2INTRH0hSee AON_BATMON:TEMP.INT.
Follow this procedure to get the correct value:
- Do two dummy reads of INT.
- Then read INT until two consecutive reads are equal.
1-0FRACR0hSee AON_BATMON:TEMP.FRAC.
Follow this procedure to get the correct value:
- Do two dummy reads of FRAC.
- Then read FRAC until two consecutive reads are equal.

20.8.9.39 TIMERHALT Register (Offset = A0h) [Reset = 00000000h]

TIMERHALT is shown in Figure 20-192 and described in Table 20-214.

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Timer Halt
Debug register

Figure 20-192 TIMERHALT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPROGDLYAUX_TIMER2AUX_TIMER1AUX_TIMER0
R-0hRH/W-0hRH/W-0hRH/W-0hRH/W-0h
Table 20-214 TIMERHALT Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3PROGDLYRH/W0hHalt programmable delay.
0: AUX_EVCTL:PROGDLY.VALUE decrements as normal.
1: Halt AUX_EVCTL:PROGDLY.VALUE decrementation.
2AUX_TIMER2RH/W0hHalt AUX_TIMER2.
0: AUX_TIMER2 operates as normal.
1: Halt AUX_TIMER2 operation.
1AUX_TIMER1RH/W0hHalt AUX_TIMER01 Timer 1.
0: AUX_TIMER01 Timer 1 operates as normal.
1: Halt AUX_TIMER01 Timer 1 operation.
0AUX_TIMER0RH/W0hHalt AUX_TIMER01 Timer 0.
0: AUX_TIMER01 Timer 0 operates as normal.
1: Halt AUX_TIMER01 Timer 0 operation.

20.8.9.40 TIMER2BRIDGE Register (Offset = B0h) [Reset = 00000000h]

TIMER2BRIDGE is shown in Figure 20-193 and described in Table 20-215.

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AUX_TIMER2 Bridge

Figure 20-193 TIMER2BRIDGE Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDBUSY
R-0hR-0h
Table 20-215 TIMER2BRIDGE Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0BUSYR0hStatus of bus transactions to AUX_TIMER2.
0: No unfinished bus transactions.
1: A bus transaction is ongoing.

20.8.9.41 SWPWRPROF Register (Offset = B4h) [Reset = 00000000h]

SWPWRPROF is shown in Figure 20-194 and described in Table 20-216.

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Software Power Profiler

Figure 20-194 SWPWRPROF Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDSTAT
R-0hR/W-0h
Table 20-216 SWPWRPROF Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0STATR/W0hSoftware status bits that can be read by the power profiler.