SWCU185F january 2018 – march 2023 CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1
The VIMS provides arbitration between the CPU and the system bus. The arbitration is configurable between round-robin and static, through the VIMS:CTL.ARB_CFG register. The static arbitration is enabled by default and gives the CPU priority over the system bus.
The system arbiter allows accesses to occur simultaneously, provided that the CPU and the system bus have different target memories. If, for example, a CPU access causes a cache hit, a system bus access can access the FLASH simultaneously.