SWCU191 February 2022 CC1311P3 , CC1311R3 , CC2651P3 , CC2651R3 , CC2651R3SIPA
This section lists and describes the Arm® Cortex®-M4 registers, in the order listed in Figure 3-3. The core registers are not memory mapped and are accessed by register name rather than offset.
The register type shown in the register descriptions refers to type during program execution in thread mode and handler mode. Debug access can differ.