SWRA495L December   2015  – April 2025 CC1310 , CC1350 , CC2620 , CC2630 , CC2640 , CC2640R2F , CC2640R2F-Q1 , CC2642R-Q1 , CC2650 , CC2662R-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Oscillator and Crystal Basics
    1. 1.1 Oscillator Operation
    2. 1.2 Quartz Crystal Electrical Model
      1. 1.2.1 Frequency of Oscillation
      2. 1.2.2 Equivalent Series Resistance
      3. 1.2.3 Drive Level
      4. 1.2.4 Crystal Pulling
    3. 1.3 Negative Resistance
    4. 1.4 Time Constant of the Oscillator
  5. 2 Overview of Crystal Oscillators for CC devices
    1. 2.1 24MHz and 48MHz Crystal Oscillator
    2. 2.2 24MHz and 48MHz Crystal Control Loop
    3. 2.3 32.768kHz Crystal Oscillator
  6. 3 Selecting Crystals for the CC devices
    1. 3.1 Mode of Operation
    2. 3.2 Frequency Accuracy
      1. 3.2.1 24MHz and 48MHz Crystal
      2. 3.2.2 32.768kHz Crystal
    3. 3.3 Load Capacitance
    4. 3.4 ESR and Start-Up Time
    5. 3.5 Drive Level and Power Consumption
    6. 3.6 Crystal Package Size
  7. 4 PCB Layout of the Crystal
  8. 5 Measuring the Amplitude of the Oscillations of Your Crystal
    1. 5.1 Measuring Start-Up Time to Determine HPMRAMP1_TH and XOSC_HF_FAST_START
  9. 6 Crystals for CC13xx, CC26xx, CC23xx and CC27xx
  10. 7 High Performance BAW Oscillator
  11. 8 CC23XX and CC27XX Software Amplitude Compensation
  12. 9 Internal Capacitor Array for CC23XX and CC27XX
  13. 10Internal Capacitor Array for CC13xx and CC26xx
  14. 11Summary
  15. 12References
  16. 13Revision History

4 PCB Layout of the Crystal

The layout of the crystal can reduce the parasitic capacitance and, more importantly, reduce noise from coupling on the input of the oscillators. Noise on the input of the oscillator can lead to severe side effects such as clock glitches, flash corruption, or system crashes because the CC26xx and CC13xx devices rely on the crystal oscillators as the high- and low-frequency system clock.

The following are a few recommendations for the layout of the crystals:

  • Place the crystal as close as possible to the device to minimize the length of the PCB traces. (This placement reduces crosstalk and minimizes EMI.)
  • TI recommends a solid ground plane under the crystal.
  • Make sure no high-speed digital signals are close to the crystal to minimize cross-coupling of noise into the oscillator.

Figure 4-1 shows the top layer of the layout of the CC26xx reference design. The bottom layer is a solid ground plane. For more details, see the SimpleLink™ CC2650 EVM Kit 4XD (CC2650EM-4XD) v1.0.3 Design Files. The same crystal layout can be used with CC13xx device.

Layout of the CC26xx EVMFigure 4-1 Layout of the CC26xx EVM