SWRA640G December   2018  – September 2022 CC1310 , CC1312R , CC1314R10 , CC1350 , CC1352P , CC1352R , CC1354P10 , CC1354R10 , CC2620 , CC2630 , CC2640 , CC2640R2F , CC2640R2F-Q1 , CC2642R , CC2642R-Q1 , CC2650 , CC2652P , CC2652R , CC2652R7 , CC2652RB , CC2652RSIP , CC2662R-Q1 , CC2674P10 , CC2674R10

 

  1.   Trademarks
  2.   CC13xx/CC26xx Hardware Configuration and PCB Design Considerations
  3. 1 Reference Design
    1. 1.1 Sub-1 GHz LaunchPads
      1. 1.1.1 LAUNCHXL-CC1310
      2. 1.1.2 LAUNCHXL-CC1312R
    2. 1.2 2.4 GHz LaunchPads
      1. 1.2.1 LAUNCHXL-CC2640R2
      2. 1.2.2 LAUNCHXL-CC26x2R
    3. 1.3 Dual-Band LaunchPads
      1. 1.3.1 LAUNCHXL-CC1350EU/US
      2. 1.3.2 LAUNCHXL-CC1350-4
      3. 1.3.3 LAUNCHXL-CC1352R
      4. 1.3.4 LAUNCHXL-CC1352P1
      5. 1.3.5 LAUNCHXL-CC1352P-2
      6. 1.3.6 LAUNCHXL-CC1352P-4
    4. 1.4 Reference Design Overview
  4. 2 Front-End Configurations
    1. 2.1 CC13xx/CC26xx
    2. 2.2 Configuring Front-End Mode
    3. 2.3 CC13xx Single-Ended Mode
      1. 2.3.1 Single-Ended RX/TX
      2. 2.3.2 Single-Ended TX Only
      3. 2.3.3 Single-Ended RX Only
      4. 2.3.4 Single-Ended 2.4 GHz
    4. 2.4 CC26xx
  5. 3 Schematic
    1. 3.1 Schematic Overview
      1. 3.1.1 24/48 MHz Crystal
      2. 3.1.2 32.768 kHz Crystal
      3. 3.1.3 Balun
      4. 3.1.4 Filter
      5. 3.1.5 RX_TX Pin
      6. 3.1.6 Decoupling Capacitors
      7. 3.1.7 Antenna Components
      8. 3.1.8 RF Shield
      9. 3.1.9 I/O Pins Drive Strength
    2. 3.2 Bootloader Pins
    3. 3.3 AUX Pins
      1. 3.3.1 CC26x2/CC13x2 AUX Pins
      2. 3.3.2 CC26x0/CC13x0 AUX Pins
    4. 3.4 JTAG Pins
  6. 4 PCB Layout
    1. 4.1  Board Stack-Up
    2. 4.2  Balun
    3. 4.3  LC Filter
    4. 4.4  Decoupling Capacitors
    5. 4.5  Placement of Crystal Load Capacitors
    6. 4.6  Current Return Path
    7. 4.7  DC/DC Regulator
    8. 4.8  Antenna Matching Components
    9. 4.9  Transmission Lines
    10. 4.10 Electromagnetic Simulation
  7. 5 Antenna
    1. 5.1 Single-Band Antenna
    2. 5.2 Dual-Band Antenna
      1. 5.2.1 Dual-Band Antenna Match Example: 863-928 MHz and 2.4 GHz
      2. 5.2.2 Dual-Band Antenna Match: 433-510 MHz and 2.4 GHz
  8. 6 Crystal Tuning
    1. 6.1 CC13xx/CC26xx Crystal Oscillators
    2. 6.2 Crystal Selection
    3. 6.3 Tuning the LF Crystal Oscillator
    4. 6.4 Tuning the HF Oscillator
  9. 7 TCXO Support
    1. 7.1 Hardware
    2. 7.2 Software
    3. 7.3 Example: Usage of TCXO on CC1312R Launchpad
  10. 8 Integrated Passive Component (IPC)
  11. 9 Optimum Load Impedance
  12. 10PA Table
  13. 11Power Supply Configuration
    1. 11.1 Introduction
    2. 11.2 DC/DC Converter Mode
    3. 11.3 Global LDO Mode
    4. 11.4 External Regulator Mode
  14. 12Board Bring-Up
    1. 12.1 Power On
    2. 12.2 RF Test: SmartRF Studio
    3. 12.3 RF Test: Conducted Measurements
      1. 12.3.1 Sensitivity
      2. 12.3.2 Output Power
    4. 12.4 Software Bring-Up
    5. 12.5 Hardware Troubleshooting
      1. 12.5.1 No Link: RF Settings
      2. 12.5.2 No Link: Frequency Offset
      3. 12.5.3 Poor Link: Antenna
      4. 12.5.4 Bluetooth Low Energy: Device Does Advertising But Can Not Connect
      5. 12.5.5 Poor Sensitivity: DCDC Layout
      6. 12.5.6 Poor Sensitivity: Background noise
      7. 12.5.7 High Sleep Power Consumption
  15. 13References
  16. 14Revision History

11.2 DC/DC Converter Mode

GUID-E3B06618-16E5-4E2D-A4D6-45745F300A13-low.gifFigure 11-1 DC/DC Mode

Maximum efficiency is obtained by using the internal DC/DC converter, and it requires an external inductor (LDCDC) and capacitor (CDCDC). The components should be placed as close as possible to the CC13xx/CC26xx device and it is important to have a short current return path for from the CDCDC ground to the pad on the chip (see Section 4.7). In addition, the bulk capacitor on VDDS should be placed close to the VDDS_DCDC-pin. The actual value of LDCDC, CDCDC and CBULK vary from device to device. For the actual values, see the device-specific reference design.

When operating in DC/DC mode, the power system dynamically switches between the Global LDO and DC/DC converter depending on the required load to achieve maximum efficiency. If VDDS drops below 2.0 V, the DC/DC converter will be less efficient than the LDO and the device will run in global LDO mode. For systems operating with VDDS less than 2.0 V, consider either global LDO or external regulator mode to save component cost and board area.

The following software setup is required in the CCFG to use the DC/DC converter:

#ifndef SET_CCFG_MODE_CONF_DCDC_RECHARGE       
#define SET_CCFG_MODE_CONF_DCDC_RECHARGE       0x0   // Use the DC/DC during recharge in powerdown
// #define SET_CCFG_MODE_CONF_DCDC_RECHARGE    0x1   // Do not use the DC/DC during recharge in powerdown
#endif
#ifndef SET_CCFG_MODE_CONF_DCDC_ACTIVE
#define SET_CCFG_MODE_CONF_DCDC_ACTIVE         0x0   // Use the DC/DC during active mode
// #define SET_CCFG_MODE_CONF_DCDC_ACTIVE      0x1   // Do not use the DC/DC during active mode
#endif