SWRZ171 July   2025 CC2755R10

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Advisories Matrix
  5. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support—Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  6. 3Advisories
    1. 3.1  ADC_08
    2. 3.2  ADC_09
    3. 3.3  BATMON_01
    4. 3.4  BATMON_02
    5. 3.5  SYS_204
    6. 3.6  SYS_206
    7. 3.7  SYS_207
    8. 3.8  APU_201
    9. 3.9  UDMA_01
    10. 3.10 RADIO_05

3.9 UDMA_01

μDMA write response to a peripheral’s single request can be missed.

Revisions Affected

F

Details

μDMA responds to single and burst requests from peripherals. In case the write access(es) from μDMA is(are) intercepted by the interconnect write buffers due to arbitration loss, the peripheral can raise a second spurious single or burst request. Since the μDMA responds to the second request after the peripheral’s FIFO gets full with earlier write buffer contents, the second write(s) is(are) ignored by the peripheral and get(s) missed. This issue is seen only during data transfers via μDMA TX channels. This issue is not seen on the μDMA RX channels, since the read path through the interconnect does not include write buffers.

Workaround

μDMA SETBURST is configured to use BURST requests.

μDMA arbitration size is 2.

The TX FIFO level trigger is set to ≤ 1/4 empty.

This workaround is incorporated into the SimpleLink™ Low Power F3 software development kit (SDK) version 9.11 and newer.