In Figure 3-3 relation shows how the different cores work together. The complete frame handling is done using one Industrial communication subsystem (ICSS), including the cycle-time generation. The stack itself is implemented in a single Arm® core.

PRU0 implements the framehandler, responsible for sending and receiving frames on all eight ports. After the internal state machine has completed, an interrupt is sent to the second PRU core.

This interrupt is used for generating the cycle timing. PRU1 holds a counting register, and for each port a compare register as well as some status and control bits. Here the cycle time is configured and as soon as it is time for sending the next frame, a trigger is sent to PRU0 to send out a frame.

The Arm core controls both PRUs. During start-up, the cycle timer is not yet used and frames are sent out manually through PRU0 and triggering the Tx from the Arm core. When switching to operational mode and the exchange of process data begins, PRU1 gets configured to the right cycle time and takes over to control the trigger for sending data. The Arm core in this case gets an interrupt after each frame has been sent and the answer from a device is received or a timeout has occurred.

With the scheme, the cycle time is independent from the CPU load on the Arm core. Also the load is reduced as the timing does not need to be generated there.