TIDUCU8A september   2022  – may 2023

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Framehandler
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Power Supply Inrush Tests (TCM_PHYL_INTF_ISIRM)
      2. 3.3.2 Interface Wake-Up Voltages (TCM_PHYL_INTF_IQWUH and TCM_PHYL_INTF_IQWUHL)
      3. 3.3.3 Current Sink
      4. 3.3.4 Timing Tests
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5Revision History

Description

This design implements an IO-Link Master with fast and deterministic timing with eight ports. Each port can be operated with independed bit rate and cycle timing. This design can be used to build a remote IO gateway to connect to OPC UA, Profinet, EtherCAT, or Ethernet IP. A PRU based frame handler provides a flexible way to of timing and synchronization.