TIDUDS9B December   2017  – November 2022

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Conditions of Use: Assumption
        1. 2.2.1.1 Generic Assumptions
        2. 2.2.1.2 Specific Assumptions
      2. 2.2.2 Diagnostics Coverage
        1. 2.2.2.1 Dual-Channel Monitoring
        2. 2.2.2.2 Checking ISO1211 Functionality With MCU (SIL1)
        3. 2.2.2.3 Checking TPS22919 Functionality With MCU (SIL1)
        4. 2.2.2.4 Checking TPS27S100 Functionality With MCU (SIL1)
        5. 2.2.2.5 Optional Monitoring Using RDY Pin of ISO5452, ISO5852S or UCC21750 Integrated Analog-to-PWM Isolated Sensor
      3. 2.2.3 Drive State
    3. 2.3 Highlighted Products
      1. 2.3.1 ISO1211
      2. 2.3.2 TPS27S100
      3. 2.3.3 TPS22919
      4. 2.3.4 ISO5852S, ISO5452
    4. 2.4 System Design Theory
      1. 2.4.1 Digital Input Receiver for STO
      2. 2.4.2 STO_1 Signal Flow Path for Controlling VCC1
      3. 2.4.3 STO_2 Signal Flow Path
        1. 2.4.3.1 High-Side Switch for Controlling Secondary-Side Supply Voltage of Gate Driver
        2. 2.4.3.2 Powering up Secondary Side: VCC2 of Gate Driver
      4. 2.4.4 Gate Driver Design
      5. 2.4.5 STO_FB Signal Flow Path
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Getting Started Hardware
      1. 3.1.1 PCB Overview
    2. 3.2 Testing and Results
      1. 3.2.1 Logic High and Logic Low STO Thresholds
      2. 3.2.2 Validation of STO1 Signal
        1. 3.2.2.1 Propagation of STO1 to VCC1 of Gate Driver
        2. 3.2.2.2 1-ms STO Pulse Rejection
        3. 3.2.2.3 Diagnostic Pulses From MCU Interface
      3. 3.2.3 Validation of STO2 Signals
        1. 3.2.3.1 Propagation of STO2 to VCC2 of Gate Driver
        2. 3.2.3.2 1-ms Pulse Rejection
        3. 3.2.3.3 Diagnostic Pulses From MCU
        4. 3.2.3.4 Inrush Current Measurement
      4. 3.2.4 3.3-V Voltage Rail From Switcher
      5. 3.2.5 60-V Input Voltage and Reverse Polarity Protection
      6. 3.2.6 Validation of Trip Zone Functionality
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 Layer Plots
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Related Documentation
    1. 5.1 Trademarks
  11. 6About the Author
  12. 7Recognition
  13. 8Revision History

3.2 Testing and Results

Note: The test results in this chapter were all tested based on RevE1.0 board. Table 3-5 lists all the design change from Rev E1.0 to Rev E2.1.
Table 3-5 Design Change Log for Rev E2.1
NUMBERREVISIONDOC. REF.CHANGE DESCRIPTION

1

E2.1

Schematic and BOM

Change U5 (dual channel isolator ISO1212) to 2 single channel isolator U5 and U9 (ISO1211) to achieve a hardware fault tolerance of 1 (HFT=1).

2

E2.1Schematic and BOMRemove U4, U6 (TVS3300) on the input of isolator since ISO1211 with Rsense=562W and Rth=2.5kW supports ±1kV surge. Refer to ISO1211 data sheet Table 3.

3

E2.1Schematic and BOM

Add 2nd clamp circuit (R46, C37, Q3) for the STO 1 output VCC (Gate driver logic power).

This prevents reverse bias of the VCC supply through the CMOS input gate driver ISO5852S (or ISO5452) in case the PWM signals are still active high (3V3).

4

E2.1Schematic and BOMAdd isolated 24 STO_FB output circuit to provide indication of the drive’s status (safe state or normal operation). Can be used to feedback the drive’s status to a safety PLC for additional diagnostics, if desired.

5

E2.1Schematic and BOMChange all the capacitors (MLCC) which design state is” obsolete” or” not for new design” to the parts with” Active” status.

6

E2.1Schematic and BOMChange indication LED D7 which design state is” obsolete” to the part with” Active” status. Change R31 from 50ohm to 200ohm according to new D7 rated current.

7

E2.1Schematic and BOM

Load switch U7 change from TPS22860 to TPS22919 to overcome the input pin open fault:

  • TPS22860 input open|Hiz --> will lead un-determinate state of the output.

  • TPS22919 input open|Hiz --> will not pass through voltage to OUT.

8

E2.1

Schematic and BOM

Change single U2 (4 channels logic gate SN74HC7001DT) to dual separate logic gates U2 and U10 (SN74LVC2G132YZPR) to achieve HFT=1.

9

E2.1Schematic and BOM

Separate R13 (1kohm) to R6 and R13 (2*499ohm).

Separate R20 (1kohm) to R17 and R20 (2*499ohm).

To get rid of the short|change value failure mode of resistor which will bypass the filter for logic gate.

10

E2.1Schematic and BOM

Change J2 from OST ED555/3DS to PHX 1751251.

Easier for assembly cables with bigger screw holes.

11

E2.1SchematicAdd line around the STO_1 and STO_2 circuits and exclude the power supply. Add note for PSU that not part of the TUEV concept review, needs to be a protected supply. (refer to TIDA-01599_STO_Concept_FMEA_1v6.docx)

12

E2.1SchematicAdd requirements for power rails to schematic (refer to TIDA-01599_STO_Concept_FMEA_1v6.docx)

13

E2.1Schematic and BOMChange R15, R22 to surge proof MELF, change C8, C11 voltage rating to 100V

14

E2.1

Layout

Change layout and board dimension according to above modification.

15

E2.1

Layout

Swap POWER layer (mid layer 2) and Ground layer (mid layer 1) to have a proper return ground for the high-speed signals on TOP layer.