TIDUDS9B December   2017  – November 2022

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Conditions of Use: Assumption
        1. 2.2.1.1 Generic Assumptions
        2. 2.2.1.2 Specific Assumptions
      2. 2.2.2 Diagnostics Coverage
        1. 2.2.2.1 Dual-Channel Monitoring
        2. 2.2.2.2 Checking ISO1211 Functionality With MCU (SIL1)
        3. 2.2.2.3 Checking TPS22919 Functionality With MCU (SIL1)
        4. 2.2.2.4 Checking TPS27S100 Functionality With MCU (SIL1)
        5. 2.2.2.5 Optional Monitoring Using RDY Pin of ISO5452, ISO5852S or UCC21750 Integrated Analog-to-PWM Isolated Sensor
      3. 2.2.3 Drive State
    3. 2.3 Highlighted Products
      1. 2.3.1 ISO1211
      2. 2.3.2 TPS27S100
      3. 2.3.3 TPS22919
      4. 2.3.4 ISO5852S, ISO5452
    4. 2.4 System Design Theory
      1. 2.4.1 Digital Input Receiver for STO
      2. 2.4.2 STO_1 Signal Flow Path for Controlling VCC1
      3. 2.4.3 STO_2 Signal Flow Path
        1. 2.4.3.1 High-Side Switch for Controlling Secondary-Side Supply Voltage of Gate Driver
        2. 2.4.3.2 Powering up Secondary Side: VCC2 of Gate Driver
      4. 2.4.4 Gate Driver Design
      5. 2.4.5 STO_FB Signal Flow Path
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Getting Started Hardware
      1. 3.1.1 PCB Overview
    2. 3.2 Testing and Results
      1. 3.2.1 Logic High and Logic Low STO Thresholds
      2. 3.2.2 Validation of STO1 Signal
        1. 3.2.2.1 Propagation of STO1 to VCC1 of Gate Driver
        2. 3.2.2.2 1-ms STO Pulse Rejection
        3. 3.2.2.3 Diagnostic Pulses From MCU Interface
      3. 3.2.3 Validation of STO2 Signals
        1. 3.2.3.1 Propagation of STO2 to VCC2 of Gate Driver
        2. 3.2.3.2 1-ms Pulse Rejection
        3. 3.2.3.3 Diagnostic Pulses From MCU
        4. 3.2.3.4 Inrush Current Measurement
      4. 3.2.4 3.3-V Voltage Rail From Switcher
      5. 3.2.5 60-V Input Voltage and Reverse Polarity Protection
      6. 3.2.6 Validation of Trip Zone Functionality
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 Layer Plots
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Related Documentation
    1. 5.1 Trademarks
  11. 6About the Author
  12. 7Recognition
  13. 8Revision History

2.2.1.2 Specific Assumptions

  • Input signals STO_1 and STO_2.
  1. Input voltage is between 0-V and 24-V nominal with worst case of 3.6-V as logic low and 20.4-V as logic high. No intermediate voltage is expected.
  2. The logic low (diagnostic pulse) in the STO signal is assumed either to be less than 1ms or greater than 2ms. No intermediate values are allowed.
  • Diagnostic coverage of STO_1 and STO_2 and STO_FB subsystems
  1. The MCU and the related diagnostic software is excluded in the analysis and is assumed to be developed in accordance with functional safety requirements. The MCU is assumed SIL 1 certified and the software implemented accordingly to meet at least SIL 1.
  • Output signal STO_FB:
  1. The output voltage is assumed to be between 0-V and 24-V nominal with worst case of 3.6-V as logic low and 20.4-V as logic high. The external supply voltage to the 24V STO_FB is assumed to be protected against over-voltage and is required to remain within 24V ±20% tolerance.
  • Power supply rails of STO_1 and STO_2 subsystem
  1. P3V3 supply: Assumed to be protected against fault, remains within ±20% tolerance (3.9 V maximum, 2.7 V minimum. If out of spec, it will be shut down to 0V. When a single protected power supply is used for both STO_1 and STO_2 subsystems, it shall employ two independent protection circuits (HFT = 1).
  2. 24-V supply: The 24V input supply for the P24V is assumed to be protected against fault and remains within ±20% tolerance. If out of spec, it will be shut down to 0V.
  • Isolated gate drive supply TIDA-00199
  1. It is assumed that the quad output rails (VCC2 = +15 V, VEE2 = –8 V) decay to 0 V within less than 10 ms, after the P24V DC input voltage was disconnected.
  2. It is assumed that all faults with TIDA-00199 are safe and yield to a 0V output voltage for all quad output rails VCC2 and VEE2.
  • Temperature
  1. It is assumed the components operate within the recommended operating temperature range. A temperature sensor is required to be added and if the ambient temperature is outside the recommended operating range all safety relevant supplies will be shutdown. This circuit is not part of this design.