TIDUE73A April   2018  – November 2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 C2000 Real-Time MCU LaunchPad
      2. 2.2.2 SN65HVD78
      3. 2.2.3 TLV702
      4. 2.2.4 TPS22918-Q1
    3. 2.3 Design Considerations
      1. 2.3.1 BiSS-C Protocol
        1. 2.3.1.1 Line Delay Compensation
        2. 2.3.1.2 Processing Time Request by Encoder
        3. 2.3.1.3 Control Communication
      2. 2.3.2 C2000 BiSS-C Encoder Interface Overview
      3. 2.3.3 TIDM-1010 Board Implementation
      4. 2.3.4 MCU Resource Requirements
        1. 2.3.4.1 Input, Output Signals, and CLB Tiles
      5. 2.3.5 CLB BiSS-C Implementation Details
        1. 2.3.5.1 Transaction Waveforms
        2. 2.3.5.2 FRAME_STATE Generation
        3. 2.3.5.3 CLB_SPI_CLOCK Generation
        4. 2.3.5.4 ENCODER_CLOCK (MA) Generation
      6. 2.3.6 PM BiSS-C Interface Library
        1. 2.3.6.1 PM BiSS-C Library Functions
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware
      1. 3.1.1 TIDM-1010 Jumper Configuration
    2. 3.2 Software
      1. 3.2.1 C2000 Driver Library (DriverLib)
      2. 3.2.2 C2000 SysConfig
      3. 3.2.3 C2000 Configurable Logic Block Tool
      4. 3.2.4 Installing Code Composer Studio™ and C2000WARE-MOTORCONTROL-SDK
      5. 3.2.5 Locating the Reference Software
    3. 3.3 Testing and Results
      1. 3.3.1 Hardware Configuration
      2. 3.3.2 Building and Loading Project
      3. 3.3.3 Running Example Code
      4. 3.3.4 Encoder Test
      5. 3.3.5 Benchmarks
      6. 3.3.6 Troubleshooting
  10. 4Design Files
  11. 5Software Files
  12. 6Related Documentation
    1.     Trademarks
  13. 7Terminology
  14. 8About the Authors
  15. 9Revision History

2.3.4 MCU Resource Requirements

Table 2-3 lists the C2000 Real-Time MCU resources used by the TIDM-1010 reference design.

Table 2-3 TIDM-1010 Resource Usage
RESOURCE NAME and Quantity TYPE PURPOSE
CLB x 2 Type 1 or later Provides the SPI clock, delay compensation, and CDM bit control. If the tile instance is changed, then routing in/out of the CLB must also be updated.
GPIO x 3 I/O
  • CLB output, MA encoder clock
  • CLB output, RS-485 direction control (TxEN). For BiSS-C this signal is held low.
  • CPU encoder power control (PwrCtl). This signal is not required if the encoder power is controlled in another manner (example: externally powered).
GPIO x 1 I/O (F2837xD, F2837xS and F28007x only)
  • CLB output of CLB_SPI_CLK
  • CLB Type 1: route this pin externally to the SPICLK input.
  • CLB Type 2, or later: clock the SPI module directly from the CLB. An external connection is not required, but can be useful for test and debug.
INPUTXBAR or CLB_INPUTXBAR x 1 Module, I/O Connect the SPI PICO pin to the CLB input.
OUTPUTXBAR or CLB_OUTPUTXBAR or CLB override of peripheral output x 2 Module, I/O
  • Connect a CLB output to ENCODER_CLOCK (MA) GPIO
  • Connects the CLB to TxEN GPIO
SPI x 1 Module and I/Os One SPI instance to receive the RS-485 physical layer data signal. The SPI clock is controlled by the CLB.
CPU and Memory Module CPU and memory use for various functions.