TIDUEG2C March 2019 – March 2020
3.1.1 Hardware Settings
The design follows a High-Speed Edge Card (HSEC) control card concept, and any device for which a HSEC control card is available from the C2000 MCU product family can be potentially used on this design. The key resources used for controlling the power stage on the microcontroller are listed in Table 2. Figure 26 shows the key power stage and connectors on the reference design. Table 3 lists the key connectors and their functions. To get started:
- Make sure no power source is connected to the board.
- Insert the control card in the J202-J207 slot.
- Connect a power source (but do not power up) for the primary and secondary side (+5 V, 2 A) at the test points shown in Figure 26.
- Now, switch the power source on for both the primary and secondary side. A green LED on the control card will light up. This indicates the C2000 MCU device is powered. Note: The bias for the microcontroller is separated from the power stage; this enables a safe bringup of the system in this set of instructions.
- To connect JTAG, use a USB cable from the control card and connect it to a host computer.
- A DC power supply must be connected (but not powered up) for the primary side voltage (VPRIM) across J100 and J103. Typical power rating for this supply is: VDC 350 V–600 V, Power 6.6 kW. However, a lower-rating supply can be used in the case where only low-power tests are being conducted.
- A second DC power source is needed to emulate a battery voltage lab, and can be connected (but not powered up) to J101-J102 to provide the secondary side voltage (VSEC).
- Mechanism to load the secondary side is needed for an appropriate power level. For example, for a 300-V, 4-kW test, a resistive load of ~22.5 Ω is needed.
- Current and voltage probes can be connected to observe the tank current at primary and secondary. Optionally, a power meter can be connected to measure the efficiency.
Figure 26. Board Overview
Table 2. Key Controller Peripherals Used for Control of the Power Stage on the Board
| SIGNAL NAME | HSEC PIN NUMBER | FUNCTION |
|---|---|---|
| PWM-1A | 49 | PWM : PRIM_LEG1_H (Primary side leg 1, high side switch) |
| PWM-1B | 51 | PWM : PRIM_LEG1_L ((Primary side leg 1,low side switch) |
| PWM-2A | 53 | PWM : PRIM_LEG2_H (Primary side leg 2, high side switch) |
| PWM-2B | 55 | PWM : PRIM_LEG2_L ((Primary side leg 2,low side switch) |
| PWM-3A | 50 | PWM : SEC_LEG1_H (Secondary side leg 1, high side switch) |
| PWM-3B | 52 | PWM : SEC_LEG1_L (Secondary side leg 1, low side switch) |
| PWM-4A | 54 | PWM : SEC_LEG2_H (Secondary side leg 2, high side switch) |
| PWM-4B | 56 | PWM : SEC_LEG2_L (Secondary side leg 2, low side switch) |
| VDAC_PGA | 9 | DAC: 1.65 reference generated for on chip PGA bases sensing of IPRIM |
| VSEC | 14 | ADC |
| IPRIM | 15 | PGA + |
| VPRIM | 18 | ADC |
| IPRIM_TANK | 21 | ADC with CMPSS (dual mapped) |
| IPRIM_TANK_2 | 23 | ADC with CMPSS (dual mapped) |
| ISEC_TANK | 24 | ADC with CMPSS (dual mapped) |
| IPRIM_TANK_2 | 25 | ADC with CMPSS (dual mapped) |
| ISEC | 27 | ADC with CMPSS |
| IPRIM_TANK | 28 | ADC with CMPSS (dual mapped) |
| ISEC_TANK | 34 | ADC with CMPSS (dual mapped) |
| PRI_FAULT | 74 | GPIO : IO flag for the primary side |
| SCI_RX | 76 | GPIO : Communication to PFC controller |
| SCI_TX | 78 | GPIO : Communication to PFC controller |
Table 3. Key Connectors and Their Function
| CONNECTOR NAME | FUNCTION |
|---|---|
| J100-J103 | Primary power connection |
| J101-J102 | Secondary power connection |
| J203 | Connection for communication to the PFC controller |
| J202-J207 | HSEC control card connector slot |
Specific to the F28004x device, the following IOs are used in the code:
- Profiling code, ISR1, ISR2, ISR3 → GPIO40 (HSEC pin 68), GPIO11 (HSEC pin 70), GPIO16 (HSEC pin 67)
- Debugging active synchronous rectification, the CMPSS output is brought out on XBAR1 and XBAR2 → GPIO58 (HSEC pin 99), GPIO59 (HSEC pin 101)