TIDUEZ8C december   2022  – june 2023

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Insulation Monitoring
    2. 1.2 Impact of Parasitic Isolation Capacitance
    3. 1.3 IEC 61557-8 Standard for Industrial Low-Voltage Distribution Systems
    4. 1.4 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 TPSI2140
      2. 2.2.2 AMC3330
      3. 2.2.3 TPS7A24
      4. 2.2.4 REF2033
      5. 2.2.5 TLV6001
    3. 2.3 Design Considerations
      1. 2.3.1 Resistive Bridge
      2. 2.3.2 Isolated Analog Signal Chain
        1. 2.3.2.1 Differential to Single-Ended Conversion
        2. 2.3.2.2 High-Voltage Measurement
        3. 2.3.2.3 Signal Chain Error Analysis
      3. 2.3.3 Loss of PE Detection
      4. 2.3.4 Insulation Monitoring on AC Lines
      5. 2.3.5 PCB Layout Recommendations
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 Connectors
      2. 3.1.2 Default Jumper Configuration
      3. 3.1.3 Prerequisites
    2. 3.2 Software Requirements
    3. 3.3 Software
    4. 3.4 Test Setup
    5. 3.5 Test Results
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Documentation Support
    3. 4.3 Support Resources
    4. 4.4 Trademarks
  11. 5About the Author
  12. 6Revision History

1.2 Impact of Parasitic Isolation Capacitance

In an unearthed power distribution system, the isolation barrier protects the user and components sitting on the low-voltage side by preventing high currents flowing to protective earth. The isolation barrier is expected to be of a resistive nature. Nevertheless, some factors such as improper earth connection or humidity can increase the isolation capacitance to earth of the system.


GUID-20210809-SS0I-BRJD-H98Q-BVT2D3TZPDL5-low.svg

Figure 1-7 Isolation Barrier Capacitance Effect on Insulation Monitoring Device

In this system, under proper operation or asymmetrical fault of the isolation barrier, this static capacitance to earth forces a delay in the settling time of the isolation voltage when the resistive branch is switched in. A period of wait time must occur after the resistive branch is switched in and before the measurement of the insulation voltage is done. This reduces overall measurement speed in systems with higher insulation capacitance. The time constant of the resulting RC circuit is shown in Equation 15, assuming RisoN is small and RisoP is high.

Equation 15. τ=(RisoP//RstP)×CisoP 

As an example, in case of a insulation capacitance of 10 nF and a RstP of 68.1 kΩ, as observed on the 400-V version of this design, and RisoP of 10 MΩ, a time constant of 676 µs is the result. A delay between the closing of the switch and the start of the measurement of at least 3 τ is recommended to let the voltage settle to 95% of the final value.

By allowing higher currents across the isolation barrier through the switched-in resistive branch, faster settling times can be achieved. The current through the switched-in branch Ist can be calculated using Equation 15

Equation 16. I st = V Bus ( R stP +   R inAMC )

Hence, consider the tradeoff between faster settling times and power dissipation when designing a resistive divider branch, while keeping the maximum allowed current in mind. Further details on the implementation in this reference design are found in Section 2.3.