TIDUEZ8 May   2021

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Insulation Monitoring
    2. 1.2 Isolation Capacitance
    3. 1.3 IEC 61557-8 Standard for Industrial Low-Voltage Distribution Systems
    4. 1.4 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 TPSI2140
      2. 2.2.2 AMC3330
      3. 2.2.3 TPS7A24
      4. 2.2.4 REF2033
      5. 2.2.5 TLV6001
    3. 2.3 Design Considerations
      1. 2.3.1 Resistive Bridge
      2. 2.3.2 Isolated Analog Signal Chain
        1. 2.3.2.1 Differential to Single-Ended Conversion
        2. 2.3.2.2 High-Voltage Measurement
        3. 2.3.2.3 Signal Chain Error Analysis
      3. 2.3.3 PCB Layout Recommendations
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 Connectors
      2. 3.1.2 Default Jumper Configuration
      3. 3.1.3 Prerequisites
    2. 3.2 Software Requirements
    3. 3.3 Test Setup
    4. 3.4 Test Results
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Documentation Support
    3. 4.3 Support Resources
    4. 4.4 Trademarks
  10. 5About the Authors

TPSI2140

The TPSI2140-Q1 is an isolated solid-state relay that utilizes TI's high reliability capacitive isolation technology in combination with internal back to back MOSFETs to form a completely integrated solution requiring no secondary side power supply. The primary side consists of four differential drivers that deliver power and enable logic information to each of the internal MOSFETs on the secondary side.

When the enable pin is brought HI, the oscillator starts causing the drivers to send power and a logic HI across the barrier. When the enable pin is brought LO, the drivers are disabled. On the secondary side, each MOSFET has a full-bridge rectifier to feed a band pass amplifier and demodulator that determines the logic state delivered by the primary side. The slew rate drivers control the gate of the MOSFET according to the logic delivered.

The avalanche robust MOSFETs and thermally conscious package design allow it to survive system-level High Potential (HiPot) Screening and DC fast charger surge currents of up to 2 mA without requiring any external components. The Thermal Avalanche Protection (TAP) feature included in the TPSI2140T-Q1 devices further improve the avalanche current capability by monitoring the junction temperature and enabling the MOSFETs to keep the temperature in a safe operating range.

Key features include:

  • AEC-Q100 qualified with –40°C to 125°C ambient operating temperature
  • Capacitive isolation barrier up to 3750 VRMS, 5300 VDC
  • 1400-V standoff voltage across secondary S1, S2 switch terminals
  • Creepage and clearance ≥ 8 mm (primary-secondary)
  • Creepage and clearance ≥ 6 mm (across S1, S2 switch terminals)
  • Low power consumption: < 5-mA input current
Figure 2-2 TPSI2140 Functional Block Diagram