TIDUF08 January   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 General Layout Recommendations
      1. 2.3.1 DLPC3436 Layout Guidelines
        1. 2.3.1.1 PLL Power Layout
        2. 2.3.1.2 I2C Interface Performance
        3. 2.3.1.3 DMD Control and Sub-LVDS Signals
        4. 2.3.1.4 Layout Layer Changes
        5. 2.3.1.5 Stubs
        6. 2.3.1.6 Terminations
        7. 2.3.1.7 Routing Vias
      2. 2.3.2 FPGA DDR2 SDRAM Interface Routing
      3. 2.3.3 DLPA2005 Layout Recommendations
        1. 2.3.3.1 Layout Guidelines
        2. 2.3.3.2 Layout Example
        3. 2.3.3.3 Thermal Considerations
      4. 2.3.4 DMD Flex Cable Interface Layout Guidelines
    4. 2.4 Highlighted Products
  9. 3Hardware
    1. 3.1 Hardware Requirements
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 Layout Files
      4. 4.1.4 Mechanical Files
    2. 4.2 Software and FPGA code
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks

2.3.3.1 Layout Guidelines

As for all chips with switching power supplies, the layout is an important step in the design, especially in the case of high peak currents and high switching frequencies. If the layout is not carefully done, the regulators can show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current paths and for the power ground tracks. Input capacitors, output capacitors, and place inductors as close as possible to the IC.

Figure 2-4 shows an example layout that has critical parts placed as close as possible to the pins. Following are recommendations for the components:

    R1is RLIM and is connected through a wide trace (low resistance) to the system ground. Star connect the analog ground at pin 5 to the point where RLIM is connected to the system ground. Aim on a wide and low-ohmic trace as well, although this one is less critical (tens of mA).
    L1is the big inductor for the VLED that is connected through two wide traces to the pins.
    C4the decoupling capacitors for the VLED. Place C4 as close as possible to the part and directly connect C4 to ground.
    L3/C20are components used for the VCORE BUCK. L3 is placed close to the pin and connected with a wide trace to the part. C20 is placed directly beside the inductor and connected to the PGND pin.
    L2This inductor is part of the DMD reset regulators and is also placed as close as possible to the DLPA2005 using wide PCB traces.