TIDUF20B December   2022  – July 2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Configure This Design for Different Use Cases
      2. 2.2.2 Auxiliary Power Strategy
      3. 2.2.3 High-Side N-Channel MOSFET
      4. 2.2.4 Stacked AFE Communication
      5. 2.2.5 Thermistor Multiplexer
      6. 2.2.6 CAN Stacking
    3. 2.3 Highlighted Products
      1. 2.3.1  BQ76972
      2. 2.3.2  MSPM0G3519
      3. 2.3.3  UCC334xx
      4. 2.3.4  LM5168
      5. 2.3.5  ISO1640
      6. 2.3.6  ISO1042
      7. 2.3.7  ISO1410
      8. 2.3.8  TPS7A24
      9. 2.3.9  TMP61
      10. 2.3.10 TPD2E007
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software Requirements
      1. 3.2.1 Getting Started MSPM0 Software
        1. 3.2.1.1 Download and Install Software Required for Board Test
        2. 3.2.1.2 Import the Project Into CCS
        3. 3.2.1.3 Compile the Project
        4. 3.2.1.4 Download Image and Run
      2. 3.2.2 Software Function List
        1. 3.2.2.1 Driverlib Function List
          1.        CAN_ID_Init_on_Startup
          2.        CAN_Write
          3.        CANprocessCANRxMsg
          4.        I2C_WriteReg
          5.        I2C_ReadReg
          6.        RS485_Send
          7.        RS485_Receive
        2. 3.2.2.2 Application Function List
          1.        Temp_Mux_Polling
          2.        BatteryDataUpdate_32s
          3.        BQ769x2_OTP_Programming
          4.        Check_Signal_Pattern
          5.        BMU_FET_Test
      3. 3.2.3 Software Workflow
    3. 3.3 Test Setup
    4. 3.4 Test Results
      1. 3.4.1 Cell Voltage Accuracy
      2. 3.4.2 Pack Current Accuracy
      3. 3.4.3 Auxiliary Power and System Current Consumption
      4. 3.4.4 Protection
      5. 3.4.5 Working Modes Transition
      6. 3.4.6 Thermistor Multiplexer
      7. 3.4.7 ESD Performance
      8. 3.4.8 Surge Immunity
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author
  12. 6Revision History

3.4.8 Surge Immunity

This design demonstrates immunity to surges in accordance with the test procedure specified in IEC61000-4-5. The tests are conducted on the DC power ports and the communication ports using the following specified test levels:

  • For DC power ports — PACK+ and PACK–: test level 4, ±2kV line-to-line, and ±4kV line-to-ground
  • For communication ports — CAN and RS-485: test level 3, ±1kV line-to-line, and ±2kV line-to-ground

The device was tested in a third-party certification lab with a real 32s battery pack attached. Table 3-5 lists the test results.

Table 3-5 Surge Performance
Open-Circuit Test Voltage APPLIED TERMINAL
PACK+ PACK– CAN0H CAN0L CAN1H CAN1L RS-485A RS-485B
Line-to-Line 1kv N/A PASS PASS PASS PASS PASS PASS

–1kv

 PASS PASS PASS PASS PASS PASS
2kV PASS PASS N/A
–2kV PASS PASS
Line-to-ground 2kV N/A PASS PASS PASS PASS PASS PASS
–2kv PASS PASS PASS PASS PASS PASS
4kV PASS PASS N/A
–4kV PASS PASS