TIDUF20B December   2022  – July 2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Configure This Design for Different Use Cases
      2. 2.2.2 Auxiliary Power Strategy
      3. 2.2.3 High-Side N-Channel MOSFET
      4. 2.2.4 Stacked AFE Communication
      5. 2.2.5 Thermistor Multiplexer
      6. 2.2.6 CAN Stacking
    3. 2.3 Highlighted Products
      1. 2.3.1  BQ76972
      2. 2.3.2  MSPM0G3519
      3. 2.3.3  UCC334xx
      4. 2.3.4  LM5168
      5. 2.3.5  ISO1640
      6. 2.3.6  ISO1042
      7. 2.3.7  ISO1410
      8. 2.3.8  TPS7A24
      9. 2.3.9  TMP61
      10. 2.3.10 TPD2E007
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software Requirements
      1. 3.2.1 Getting Started MSPM0 Software
        1. 3.2.1.1 Download and Install Software Required for Board Test
        2. 3.2.1.2 Import the Project Into CCS
        3. 3.2.1.3 Compile the Project
        4. 3.2.1.4 Download Image and Run
      2. 3.2.2 Software Function List
        1. 3.2.2.1 Driverlib Function List
          1.        CAN_ID_Init_on_Startup
          2.        CAN_Write
          3.        CANprocessCANRxMsg
          4.        I2C_WriteReg
          5.        I2C_ReadReg
          6.        RS485_Send
          7.        RS485_Receive
        2. 3.2.2.2 Application Function List
          1.        Temp_Mux_Polling
          2.        BatteryDataUpdate_32s
          3.        BQ769x2_OTP_Programming
          4.        Check_Signal_Pattern
          5.        BMU_FET_Test
      3. 3.2.3 Software Workflow
    3. 3.3 Test Setup
    4. 3.4 Test Results
      1. 3.4.1 Cell Voltage Accuracy
      2. 3.4.2 Pack Current Accuracy
      3. 3.4.3 Auxiliary Power and System Current Consumption
      4. 3.4.4 Protection
      5. 3.4.5 Working Modes Transition
      6. 3.4.6 Thermistor Multiplexer
      7. 3.4.7 ESD Performance
      8. 3.4.8 Surge Immunity
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author
  12. 6Revision History

3.3 Test Setup

Use the following procedures before running this design board. The design was constructed with 32s pack configurations. The board was tested using DC source and 2700μF electrolytic capacitor in parallel to simulate the total pack. Twenty 200Ω resistors in series are used to divide the pack voltage and simulate 32s battery cells.

  • DC source 1 configurations: 96V, 3A
  • DC source 2 configurations: two channel 48V, 0.5A
  • Electronic load configurations: 80V constant voltage (CV) mode

Figure 3-5 shows the charge process setup example.

TIDA-010247 Charge Setup Figure 3-5 Charge Setup

Figure 3-6 shows the discharge process setup example using the following conditions.

  • DC source configurations: 96V, 100A
  • Electronic load configurations: constant current (CC) mode
TIDA-010247 Discharge Setup Figure 3-6 Discharge Setup