TIDUF25A June 2023 – March 2025 ADS131M08 , MSPM0G1507
The MSPM0G3507 MCU is configured to have the CPU clock (MCLK) set at 79.87MHz and the CLK_OUT clock signal to ADS131M08 is set to 8.192MHz. The external 16.384MHz XTAL, which is feeding the PLL module and is being multiplied and divided with specific factors, generates a MCLK frequency (the CPU clock speed) of 79.87MHz.
The external 16.384MHz crystal is divided by 2 to create the 8.192MHz output frequency for CLK_OUT. An internal 32.768kHz LFOSC is used as the clock source for the auxiliary clock (RTCCLK) of the device.
All these settings are configured in the TIDA-010243.syscfg file in the software deliverable, utilizing the graphical Clock Tree configuration inside the SYSCONFIG tool.